Mentor adds verification expert News & Analysis 1/31/2006 Post a comment Harry D. Foster, chairman of Accellera's formal verification committee and chairman of the IEEE-1850 PSL working group, has joined Mentor Graphics' Design Verification and Test division as principal engineer.
Xpedion adds 64-bit support to Golden Gate simulator News & Analysis 1/30/2006 Post a comment Xpedion Design Systems released the latest version of its GoldenGate simulator, which the company said includes capabilities such as running Monte Carlo analysis on parallel machines, simulation time reduction, improved memory efficiency, improved workflow and 64-bit support.
Agilent claims faster extraction through IC-CAP Product News 1/30/2006 Post a comment Calling it a major breakthrough in device modeling speed and efficiency, Agilent Technologies said device modeling engineers are reporting extraction flow improvements of up to 50 percent when using the new modeling algorithms and data interface in the company's Integrated Circuit Characterization and Analysis Program.
I/O planning ensures IC packaging success Design How-To 1/30/2006 Post a comment Package-aware, I/O planning is becoming essential for designers of today's SoCs, says Egino Sarto, CTO at startup Rio Design Automation. He provides an overview of I/O planning and shows what designers need to know.
EDA stocks rebound from fall News & Analysis 1/27/2006 Post a comment EDA stocks bounced back nicely this week from the dramatic drop on Jan. 20, with Cadence Designs Systems and Synopsys each posting solid gains to finish the week in positive territory.
Mentor posts record 4Q results News & Analysis 1/26/2006 Post a comment Mentor Graphics reported a net income of $15.42 million on company-record fourth quarter revenue of $221.3 million, exceeding prior revenue guidance of $220 million for the quarter.
Firms expanding Japanese presence News & Analysis 1/25/2006 Post a comment Virtual system prototyping solution provider Carbon Design Systems has opened a direct sales office in Tokyo, while power consumption EDA tool vendor Azuro has contracted with a Japanese distributor.
Synopsys, Denali claim PCI Express 2.0 IP firsts News & Analysis 1/24/2006 Post a comment Synopsys claimed that its portfolio of DesignWare digital controller intellectual property for PCI Express is the first to support the evolving 2.0 version of the PCI Express specification. Rival EDA and IP vendor Denali Software followed suit by claiming that its PureSpec product is the first verification IP to support Gen II.
Tool claims dramatic reduction in OPC closure time News & Analysis 1/23/2006 Post a comment Claiming to offer optical proximity correction closure in a fraction of the time of conventional tools and methods, design-for-manufacturing startup Aprio Technologies introduced a new tool that makes available the lithography rule check repair technology used by the company's Halo-OPC product to manufacturers using third-party LRC and OPC tool sets.
Chip assembly challenges and solutions News & Analysis 1/23/2006 Post a comment Today's hierarchical design approaches complicate chip assembly, says Sierra Design CTO Shankar Krishnamoorthy. He discusses common problems with chip assembly and presents an approach to solve them.
Mentor execs recognized by IEEE News & Analysis 1/20/2006 Post a comment Mentor Graphics' Dennis Brophy and Dave Rich have received the IEEE Working Group Chairman’s Award for their contributions to the IEEE SystemVerilog standard.
Partnering startups claim DFM sign-off tool News & Analysis 1/19/2006 Post a comment Startups Nannor Technologies and Predictions Software say they have integrated their products to create a solution that can serve as a design-for-manufacturing signoff tool in much the same way as Synopsys' PrimeRail and competing tools provide signoff for timing.
Celoxica's Agility compiler supporting SystemC 2.1 News & Analysis 1/17/2006 Post a comment The latest release of Celoxica's Agility Compiler for SystemC synthesis supporting SystemC prototyping and verification can generate register-transfer level descriptions from transaction level models for popular ASIC/ system-on-chip synthesis flows and gate-level electronic design interchange ormat netlists for programmable logic devices.
DSP power management tools tout more battery life Product News 1/17/2006 Post a comment Texas Instruments new Power Optimization DSP Starter Kit enables system developers to accurately plan, analyze, manage and optimize real-time power consumption for its TMS320C55x DSPs. The kit was jointly developed by TI, Spectrum Digital, Inc. and National Instruments.
Cadence to help Russian electronics industry News & Analysis 1/17/2006 Post a comment The Moscow Institute of Electronic Technology (Miet) has chosen Cadence Design Systems as the sole provider of design technologies for helping Miet develop the Russian electronics industry and provide local startup companies better access to the global industry.
How to choose custom IC design tools News & Analysis 1/16/2006 Post a comment Looking for custom design tools? Tanner's Massimo Sivilotti discusses return on investment (ROI), the cost of doing business, and the important features to consider when comparing offerings.
PLM provider to help companies reuse information News & Analysis 1/13/2006 Post a comment Product lifecycle management software provider MatrixOne Inc. plans to release a business process application, Library Central, designed to help companies accelerate product development and delivery through knowledge reuse.
Blog Doing Math in FPGAs Tom Burke 15 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...