Enhanced Xilinx FPGA tool extends serial I/O debug capabilities Product News 1/30/2007 Post a comment Check out Xilinx's latest version of its ChipScope Pro software and Serial I/O toolkit. Version 9.1i extends serial I/O debug capabilities to support 65-nm Virtex-5LXT FPGAs. This release also delivers 60% faster clock speeds and comprehensive low-cost BERT capabilities for RocketIO multi-gigabit transceivers.
Magma expands in India, U.S. News & Analysis 1/29/2007 Post a comment EDA provider Magma Design Automation Inc. has moved to new facilities in India and the U.S. in anticipation of expanding staff and operations in both regions, the company reported Monday (Jan. 29).
Magma revenues up, but GAAP loss grows News & Analysis 1/26/2007 Post a comment Magma Design Automation reported record revenue for its third fiscal 2007 quarter ending Dec. 31, but the EDA provider continues to show heavy GAAP losses, due partially to acquisition costs.
System-in-package tools lacking, users say News & Analysis 1/25/2007 Post a comment System-in-package (SiP) design requires new EDA tool support and an integrated design flow across ICs, packages, and pc-boards, said users at a Fabless Semiconductor Association (FSA) conference Wednesday.
EMA buys Forte's Chronology division News & Analysis 1/23/2007 Post a comment Value added reseller (VAR) EMA Design Automation has purchased Forte Design Systems' Chronology division and its TimingDesigner product, an interactive timing diagram tool.
Partnership adds formal verification GUI Product News 1/23/2007 Post a comment Seeking to expand the use of formal property checking, Averant Inc. has joined forces with Axiom Design Automation to bring a graphical user interface (GUI) to Averant's Solidify formal verification tool.
Low power standards ignore CEA's power directives? Blog 1/22/2007 Post a comment If controversy is a measure of criticality, then the lack of a Low Power Standards is dooming many design in progress to failure. A letter writer suggests that EDA vendors are ignoring the users community in developing a low power standard.
Xilinx ISE handles incremental changes Product News 1/16/2007 Post a comment Designers who want to make a small change to an FPGA design typically must recompile the whole thing. To ease that burden for large FPGAs, Xilinx Inc. and Synplicity Inc. have co-developed incremental compilation technology.
Partnerships UK joins Silistix Series A round News & Analysis 1/16/2007 Post a comment Silistix Ltd., a spinoff from an asynchronous logic research group at the University of Manchester in England, has raised a further $6 million in a final closing of its Series A round, which was oversubscribed.
Defining the TLM-to-RTL Design Flow Design How-To 1/15/2007 Post a comment An emerging trend is a transaction level modeling (TLM)-to-register transfer level (RTL) design flow, though a set of requirements needs to be addressed to ensure a successful transition to this new flow.
How to maximize FPGA performance Design How-To 1/15/2007 Post a comment The more that can be done upfront with good coding styles, timing constraints definition, and resource planning, the easier it will be for the downstream tools to achieve timing requirements.
Sisvel extends MPEG patent disputes with SanDisk News & Analysis 1/12/2007 Post a comment LONDON — Italian group Sisvel, which licenses and manages several digital audio coding patents on behalf of a number of European companies such as Philips and France Telecom, is putting more pressure on MP3 player maker SanDisk to settle an increasingly acrimonious patent dispute.
The outlook for DRAMs in consumer electronics Design How-To 1/12/2007 Post a comment DDR3 SDRAM is the next DDR memory standard that is being developed as the successor to DDR2 SDRAM by the JEDEC standard committees. As an evolutionary product, the new features in DDR3 build on the DDR2 SDRAM feature set and add logical improvements to increase system bandwidth (up to 1.6Gb/s per pin) and reduce power consumption.
Mentor, EVE settle patent lawsuit News & Analysis 1/11/2007 Post a comment Mentor Graphics Corp. and emulation provider EVE Corp. have settled a previously unpublicized patent infringement lawsuit in which Mentor was the plaintiff, the companies reported Thursday (Jan. 11).
Embedded database adds RTOS support Product News 1/8/2007 Post a comment Hitachi 's Embedded Business Group is porting Entier, its relational database management system, to real-time operating systems (RTOSes) from Mentor Graphics and Wind River.
Synplicity technology aids ASIC verification Product News 1/8/2007 Post a comment Claiming a breakthrough in ASIC debugging, Synplicity Inc. this week will release details about TotalRecall, which it says will bring full debug visibility to FPGA prototypes used for ASIC verification. If successful, the technology could help FPGA prototypes rival far more expensive emulation systems.