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Content tagged with Design Tools (EDA)
posted in January 2007
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Altium Designer wins IEC DesignVision Award at DesignCon 2007
News & Analysis  
1/31/2007   Post a comment
Altium Designer unifies the design of hardware, programmable hardware, and the development of the embedded software.
Statistical timing pioneer moves to transistors
News & Analysis  
1/31/2007   Post a comment
Statistical timing provider Extreme DA has purchased Xigmix, a stealth-mode startup that offers transistor-level characterization and optimization, noted Mustafa Celik, Extreme DA CEO.
Synplicity's Certify software supports Xilinx Virtex-5 FPGAs
Product News  
1/31/2007   Post a comment
By supporting Xilinx Virtex-5 FPGAs, Synplicity's Certify software, extends the automation of the FPGE-based ASIC prototyping flow and enhances quick partitioning technology.
Altera, announces first 8-port switch development board with IEEE 1588 timing control
Product News  
1/31/2007   Post a comment
Jointly created by Altera, National Semiconductor, and MorethanIP, an 8-port switch development board with IEEE 1588 timing control accelerates design.
EDA startup Athena secures $4 million
News & Analysis  
1/30/2007   Post a comment
EDA startup Athena Design Systems, a provider of IC analysis and routing optimization tools, has secured an additional $4 million in venture capital funding.
Enhanced Xilinx FPGA tool extends serial I/O debug capabilities
Product News  
1/30/2007   Post a comment
Check out Xilinx's latest version of its ChipScope Pro software and Serial I/O toolkit. Version 9.1i extends serial I/O debug capabilities to support 65-nm Virtex-5LXT FPGAs. This release also delivers 60% faster clock speeds and comprehensive low-cost BERT capabilities for RocketIO multi-gigabit transceivers.
Magma expands in India, U.S.
News & Analysis  
1/29/2007   Post a comment
EDA provider Magma Design Automation Inc. has moved to new facilities in India and the U.S. in anticipation of expanding staff and operations in both regions, the company reported Monday (Jan. 29).
Verification box claims 200 MHz speeds
Product News  
1/29/2007   Post a comment
Gidel Ltd. claims that its new Proc_SoC rapid prototyping system can provide ASIC verification speeds of 200 MHz, thanks to a direct FPGA-to-FPGA interconnect scheme.
How to architect, design, implement, and verify low-power digital integrated circuits
Design How-To  
1/29/2007   Post a comment
To enable the adoption of advanced low-power techniques by mainstream users, there is a need for a design flow that holistically addresses the architecture, design, verification, and implementation of low-power designs.
Commentary: Models hold value, not IP
News & Analysis  
1/26/2007   Post a comment
Models hold all practical value for silicon intellectual property (IP), and are expensive to develop, manage and verify, says Calypto Design Systems' Mitch Dale (shown).
Magma revenues up, but GAAP loss grows
News & Analysis  
1/26/2007   Post a comment
Magma Design Automation reported record revenue for its third fiscal 2007 quarter ending Dec. 31, but the EDA provider continues to show heavy GAAP losses, due partially to acquisition costs.
Synplicity's DSP synthesis platform sees significant growth in 2006
News & Analysis  
1/25/2007   Post a comment
True DSP synthesis methodology and close vendor partnerships drive adoption; new wireless IP now available.
Segger Microcontroller Systems' RTOS supports ARM RealView Microcontroller Development Kit
Product News  
1/25/2007   Post a comment
RTOS tools supplier Segger Microcontroller says its embOS OS now supports the ARM RealView Microcontroller Development Kit.
System-in-package tools lacking, users say
News & Analysis  
1/25/2007   Post a comment
System-in-package (SiP) design requires new EDA tool support and an integrated design flow across ICs, packages, and pc-boards, said users at a Fabless Semiconductor Association (FSA) conference Wednesday.
EMA buys Forte's Chronology division
News & Analysis  
1/23/2007   Post a comment
Value added reseller (VAR) EMA Design Automation has purchased Forte Design Systems' Chronology division and its TimingDesigner product, an interactive timing diagram tool.
Altera's advanced signal integrity technology available through EDA partners
News & Analysis  
1/23/2007   Post a comment
Mentor Graphics is first to integrate PELE into design platform; provides an integrated suite of productivity tools for Altera's Stratix II GX FPGAs.
Xilinx announces immediate availability of Virtex-4 FX-based development platform
Product News  
1/23/2007   Post a comment
High performance FX60 FPGA with dual embedded IBM PowerPC Processors provides powerful embedded system development platform.
Xilinx Virtex-5 FPGAs and PlanAhead software honored for design innovation
News & Analysis  
1/23/2007   Post a comment
Industry's first 65nm FPGAs and design planning and analysis tool finalists in prestigious industry awards.
Partnership adds formal verification GUI
Product News  
1/23/2007   Post a comment
Seeking to expand the use of formal property checking, Averant Inc. has joined forces with Axiom Design Automation to bring a graphical user interface (GUI) to Averant's Solidify formal verification tool.
Low power standards ignore CEA's power directives?
Blog  
1/22/2007   Post a comment
If controversy is a measure of criticality, then the lack of a Low Power Standards is dooming many design in progress to failure. A letter writer suggests that EDA vendors are ignoring the users community in developing a low power standard.
Hardware generation method anticipates design reuse
News & Analysis  
1/22/2007   Post a comment
Researchers from the Indian Institute of Technology have devised an approach for hardware generation from high-level programs that they say accommodates design reuse
Test data provides yield improvement metrics
Design How-To  
1/22/2007   Post a comment
This is the first of a series of articles that covers methods to quantify yield improvement metrics to provide a way to improve the quality of DFM and DFY tools.
Q&A: DAFCA's Levin promotes post-silicon debug
News & Analysis  
1/18/2007   Post a comment
Peter Levin, CEO of EDA startup DAFCA Inc., discusses the need for post-silicon validation tools, and the challenges of selling to design teams who don't like to admit they sometimes make mistakes.
Agilent announces four low cost GENESYS configurations
Product News  
1/18/2007   Post a comment
Agilent Technologies Inc. announced four new GENESYS electronic design automation (EDA) software configurations priced under $10,000 for affordable RF circuit and system design.
Utilizing OCP to design a high performance interconnect
Design How-To  
1/18/2007   Post a comment
The OCP standard support a split transaction bus protocol that enables designers to eliminate some of the latency due to data exchanges between cores in a SoC design.
Victor Berman named Improv Systems CEO
News & Analysis  
1/18/2007   Post a comment
EDA standards guru Victor Berman has left Cadence Design Systems to take the helm at Improv Systems, a small provider of configurable DSP intellectual property (IP).
How to achieve faster compile times in high-density FPGAs
Design How-To  
1/17/2007   Post a comment
With FPGA design complexity outpacing CPU speed, FPGA designers are more dependent on design tools and methodologies that speed compile times.
EDA revenue up 17 percent, EDAC says
News & Analysis  
1/17/2007   Post a comment
The EDA industry is still on a roll, according to the EDA Consortium, with third-quarter 2006 revenue up 17 percent over the prior year quarter.
Networked audio platforms enable consumer product designs
Product News  
1/17/2007   Post a comment
BridgeCo Inc.'s newest reference design platforms based on the company's audio processor and software technology enable consumer electronics OEMs to rapidly create audio products.
How 'Design-With-Test' methods ensure low power operation
Design How-To  
1/17/2007   Post a comment
Proper use of design for test methods during the design cycle could have considerable impact on improving a device's power consumption.
Actel and Mentor expand partnership
News & Analysis  
1/16/2007   Post a comment
Actel to provide Mentor's Precision Synthesis, Actel-edition, as part of the new Libero Integrated Development Environment (IDE) 7.3 Web download product bundle.
Xilinx ISE handles incremental changes
Product News  
1/16/2007   Post a comment
Designers who want to make a small change to an FPGA design typically must recompile the whole thing. To ease that burden for large FPGAs, Xilinx Inc. and Synplicity Inc. have co-developed incremental compilation technology.

Partnerships UK joins Silistix Series A round
News & Analysis  
1/16/2007   Post a comment
Silistix Ltd., a spinoff from an asynchronous logic research group at the University of Manchester in England, has raised a further $6 million in a final closing of its Series A round, which was oversubscribed.
Address system-level HW/SW design tasks with Electronic System Level tools
Design How-To  
1/16/2007   Post a comment
To keep track of design size and complexity, designers are now looking for the next breakthrough in design productivity, implementation and verification. One answer may be electronic system level design.
Defining the TLM-to-RTL Design Flow
Design How-To  
1/15/2007   Post a comment
An emerging trend is a transaction level modeling (TLM)-to-register transfer level (RTL) design flow, though a set of requirements needs to be addressed to ensure a successful transition to this new flow.
How to maximize FPGA performance
Design How-To  
1/15/2007   Post a comment
The more that can be done upfront with good coding styles, timing constraints definition, and resource planning, the easier it will be for the downstream tools to achieve timing requirements.
Fast computation speeds signal-integrity analysis
Product News  
1/15/2007   Post a comment
Sigrity has ported its power and signal integrity analysis tools to 64-bit Linux, and has enhanced its PowerSI electrical analysis solution with parallel and distributed processing.
Latest release of Xilinx ISE software slashes FPGA design cycles
Product News  
1/15/2007   Post a comment
ISE 9.1i powered by new SmartCompile technology cuts implementation runtimes by up to 6X and delivers 30% faster performance.
Si2 approves low-power spec, seeks 'convergence'
News & Analysis  
1/12/2007   Post a comment
The Silicon Integration Initiative (Si2) has approved a Cadence Design Systems low-power IC design format specification, and will now seek to "converge" the format with a rival standards effort underway at Accellera.
The outlook for DRAMs in consumer electronics
Design How-To  
1/12/2007   Post a comment
DDR3 SDRAM is the next DDR memory standard that is being developed as the successor to DDR2 SDRAM by the JEDEC standard committees. As an evolutionary product, the new features in DDR3 build on the DDR2 SDRAM feature set and add logical improvements to increase system bandwidth (up to 1.6Gb/s per pin) and reduce power consumption.
Sisvel extends MPEG patent disputes with SanDisk
News & Analysis  
1/12/2007   Post a comment
LONDON — Italian group Sisvel, which licenses and manages several digital audio coding patents on behalf of a number of European companies such as Philips and France Telecom, is putting more pressure on MP3 player maker SanDisk to settle an increasingly acrimonious patent dispute.
New CEO pushes fast Spice innovator
News & Analysis  
1/11/2007   Post a comment
Nascentric has been slow in bringing its next-generation fast Spice technology to market, but its new CEO, Rahm Shastry, says he's going to speed things up.
Mentor, EVE settle patent lawsuit
News & Analysis  
1/11/2007   Post a comment
Mentor Graphics Corp. and emulation provider EVE Corp. have settled a previously unpublicized patent infringement lawsuit in which Mentor was the plaintiff, the companies reported Thursday (Jan. 11).
TI beefs-up MSP430-based development tool offerings
Product News  
1/11/2007   Post a comment
Targeting designers of portable, battery-powered applications, Texas Instruments has launched its new T2012 and the MSP-Mojo target boards for TI's eZ430 development tool.
Engineering software tool combines mathematical computation engine with an intuitive user-interface
Product News  
1/9/2007   Post a comment
Maplesoft's newest release of Maplesoft II features enhancements to the company's smart document interface, a strong computation engine, and connectivity capabilities. The result is an engineering software tool enables users to reduce error and dramatically increase analytical productivity.
Mentor pre-announces strong Q4 results
News & Analysis  
1/9/2007   Post a comment
Riding the crest of a strong year for the EDA industry, Mentor Graphics pre-announced record revenues and bookings for the fourth quarter of 2006.
Embedded database adds RTOS support
Product News  
1/8/2007   Post a comment
Hitachi 's Embedded Business Group is porting Entier, its relational database management system, to real-time operating systems (RTOSes) from Mentor Graphics and Wind River.
SystemVerilog adoption up, Cadence survey says
News & Analysis  
1/8/2007   Post a comment
A Cadence Design Systems user survey shows rapid growth in the adoption of SystemVerilog, with most users taking advantage of the language's assertion and testbench generation features.
Lattice and Aldec sign mixed-language simulator agreement
News & Analysis  
1/8/2007   Post a comment
Lattice becomes the only FPGA company to offer a mixed-language simulator based on Aldec's Active-HDL Designer Edition tools.
How To achieve 100% visibility with FPGA-based ASIC prototypes running at real-time speeds
Design How-To  
1/8/2007   Post a comment
Synplicity's TotalRecall technology provides a way to run FPGA-based ASIC prototypes at real-time hardware speeds while providing 100% visibility with regard to internal signals AND memory.
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