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posted in January 2008
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IBM calls for modeling standard
News & Analysis  
1/31/2008   Post a comment
The IBM-led Power.org group overseeing the Power CPU architecture is about to start an internal effort to define interface standards to link chip models with simulation tools for cores used in Power CPU-based designs, something the broader industry needs to lower design costs and shorten time-to-market, said and IBM executive.
OneSpin bites back
Programmable Logic DesignLine Blog  
1/31/2008   Post a comment
An email from Aaik van der Poe at Mentor sparks a feisty response from Michael Siegel at OneSpin.
See the World and Get your EDA Degree
Blog  
1/31/2008   Post a comment
Curricula leading to college degrees in EDA exist in Armenia and are coming in Russia and China.
FPGA-Based Prototyping - "Productivity to Burn"
Design How-To  
1/30/2008   Post a comment
This article highlights recent tool advances that can help you setup, implement, and verify your FPGA-based ASIC prototype faster than ever before.
Women in EDA Achievement Award
Design How-To  
1/30/2008   Post a comment
DAC is accepting nominations for the Marie Pistilli Women in EDA Achievment Award.
DesignCon probes high-speed signaling issues
News & Analysis  
1/30/2008   Post a comment
As signals move deeper into multi-gigabit territory, engineers are calling for more attention to the rising problems of modeling the interrelated affects of power, signaling and timing, issues that will be debated at next week's DesignCon event.
Mouser Electronics now stocking Cypress' Universal PSoC CapSense Controller Development Kit
News & Analysis  
1/29/2008   Post a comment
Development kit delivers easy prototyping and debugging for designers.
Viewpoint: Power Format Battles Over
Design How-To  
1/29/2008   Post a comment
Power management for chip design continues to be in the forefront, be it for optimization, analysis or verification. However, the power format battles have subsided and a single IEEE standard appears to be well on track.
Power Integrity and Energy Aware Floor Planning
Design How-To  
1/29/2008   Post a comment
Extreme performance and frequency are no longer dominant design goals for SoC's. Recent years have witnessed changes in microprocessors' architectures, with multi-GHz unicore CPU devices abandoned in favor of low-frequency multi-core variants, and frequency becoming a forgotten memory.
Lattice announces Service Pack 2 for its ispLEVER 7.0 FPGA design tool suite
Product News  
1/28/2008   Post a comment
ispLEVER 7.0 tool suite from Lattice includes new third-party synthesis versions, power calculator tool enhancements, and more...
Xilinx launches new XtremeDSP development kit and tools package
Product News  
1/28/2008   Post a comment
AccelDSP synthesis tool now offered with System Generator for DSP to include floating- to fixed-point conversion and architectural exploration of MATLAB algorithms.
Magma Announces Talus QDRC
Product News  
1/28/2008   Post a comment
Magma has introduced Talus QDRC to integrate design implementation and physical verification flows.
Avnet, ADI and Micron team on video surveillance development kit
Product News  
1/24/2008   Post a comment
The second generation of the Digital Video Surveillance Kit provides a simplified prototype development platform for intelligent video surveillance applications -- combining the unique video handling capabilities of the Blackfin' processor from Analog Devices and state-of-the-art CMOS image sensors from Micron Technology.
Graph-Based Physical Synthesis supports high-end Altera and Xilinx FPGAs
Product News  
1/24/2008   Post a comment
Synplicity's Synplify Premier Graph-Based Physical Synthesis technology enhanced to support Xilinx Virtex-5 FPGAs, with Beta support for Altera Stratix-II, IIGX, and III devices.
Video: Simulator hits 7 billion instructions/s
News & Analysis  
1/23/2008   Post a comment
Embedded Systems Technology Inc. believes it has hit an important milestone in systems simulation software, simulating four cars and their interactions, spanning 98 controllers running 7 billion instructions/second.
Synopsys and Acceleware Improve Optoelectronic Device Simulation
Product News  
1/23/2008   Post a comment
Acceleware Corp. and Synopsys, Inc. announced a new hardware solution that, according to the companies, enables up to 20-times faster electromagnetic simulation of optoelectronic devices such as CMOS image sensors.
Ponte Augments YA System
Product News  
1/23/2008   Post a comment
Ponte Solutions announced an enhanced YA System, version 0801, offering new defect analysis capabilities and enhanced features.
Catalytic changes name to Agility
News & Analysis  
1/23/2008   Post a comment
Catalytic's merger with Celoxica ESL Business creates algorithm-to-implementation powerhouse!
How to achieve timing-closure in high-end FPGAs
Design How-To  
1/23/2008   Post a comment
Using graph-based physical synthesis to achieve timing closure in high-capacity, high-performance FPGAs.
OneSpin Improves Language Support
Product News  
1/23/2008   Post a comment
OneSpin Solutions announced the addition of a standard assertion language link to its 360 Module Verifier solution.
Mentor Announces Accelerated Libraries for Xilinx
Product News  
1/23/2008   Post a comment
Mentor announced an accelerated library for Catapult C targeting Xilinx Virtex-5 Devices.
PrimeTime Delivers Productivity Boost
Product News  
1/23/2008   Post a comment
Synopsys, Inc. announced the 2007.12 release of its PrimeTime suite.
Catalytic Inc. Changes Name
News & Analysis  
1/23/2008   Post a comment
Catalytic Inc. today announced the company has become Agility Design Solutions Inc.
Two Interesting Books
Blog  
1/23/2008   Post a comment
Two books are reviewed. "Low Power Methodology Manual for System-On-Chip Design" and "VHDL-2008 Just the New Stuff".
Mentor unveils next generation of TestBench Xpress
Product News  
1/22/2008   Post a comment
Hardware-software co-verification platform speeds embedded software verification and accelerates simulation up to 10,000 times.
Tensilica adds support for Avnet's FPGA-based development kits
Product News  
1/22/2008   Post a comment
Avnet's Xilinx Virtex-4 LX200 development kit provides high-speed, hardware-based processor simulations of Tensilica-based designs.
Industry's highest density FPGA features 340K logic elements
Product News  
1/22/2008   Post a comment
Altera's Stratix III FPGAs (combined with Quartus II software) are claimed to enable the industry's fastest compile times per LE for faster overall timing closure.
Catapult C synthesis accelerated libraries for Virtex-5 FPGAs
Product News  
1/22/2008   Post a comment
Mentor Graphics announces Catapult C synthesis accelerated libraries for Xilinx high-performance Virtex-5 FPGAs
OneSpin adds standard assertion language link to verification solution
Product News  
1/22/2008   Post a comment
OneSpin Solutions, an electronic design automation (EDA) company, has added a standard assertion language link to its 360 Module Verifier solution.
SystemVerilog assertions open additional gateway to OneSpin's 360 MV
Product News  
1/22/2008   Post a comment
OneSpin's 360 MV formal verification solution has been augmented with support for SystemVerilog Assertions.
Video: startup explores analog EDA problems
News & Analysis  
1/22/2008   Post a comment
Startup Berkeley Design Automation is working on new capabilities to analyze in software analog effects in communications between die in a multi-chip package that can impact device yields, said company founder and chief executive Ravi Subramanian in a video interview with EE Times.
IPextreme launches new online IP store
Product News  
1/21/2008   Post a comment
Online "Core Store" streamlines licensing of valuable semiconductor IP.
Eve and CoWare link ESL to HW/SW co-verification
Product News  
1/21/2008   Post a comment
EVE-CoWare partnership ties emulation to virtual platform, thereby linking hardware/software co-verification to ESL for reduced development time.
Nios II C2H Compiler wins prestigious award
News & Analysis  
1/21/2008   Post a comment
Altera's Nios II C2H Compiler awarded Elektra '07 Embedded System Product of the Year.
Automated Formal Verification of OCP based IP Cores
Design How-To  
1/21/2008   Post a comment
Cadence's VIP library can be used to verify IP cores that implement the OCP-IP protocol, as shown in this article.
Mouser Electronics now stocking Actel IGLOO starter kits
Product News  
1/17/2008   Post a comment
Kits provide complete evaluation solutions for Actel's low-power IGLOO FPGAs.
Kazuhiro Ogawa appointed President of IPextreme Japan
News & Analysis  
1/17/2008   Post a comment
This "hot-off-the-press" news item is rather interesting to me personally as you will see...
New physical synthesis solution for Altera Stratix III FPGAs
Product News  
1/17/2008   Post a comment
Mentor announces what it claims to be the industry's first physical synthesis solution for Altera Stratix III FPGAs.
Simulation of Proprietary Low Power Wireless Systems
Design How-To  
1/17/2008   Post a comment
When developing a proprietary short-range device system, it is critical to ensure that the design meets local regulatory requirements as well as design parameters. By using a simulation tool, designers can save time and keep regulations in mind.
Xilinx ISE software and MOST NIC LogiCORE IP solution are 2008 DesignVision award finalists
News & Analysis  
1/16/2008   Post a comment
Finalists were chosen from a record number of competing products by a panel of judges selected from the 2008 DesignCon technical program committee.
Xilinx EDK delivers processing peripheral IP cores at no additional cost
Product News  
1/16/2008   Post a comment
Widely-used embedded processing IP peripherals now included at no additional charge in the Xilinx Embedded Development Kit (EDK)
Synfora meshes synthesis tool with CoWare's platform approach
Product News  
1/16/2008   Post a comment
Synthesis tool vendor Synfora Inc. said it has integrated its tools with CoWare's Platform Architect design environment.
Dynamically-reconfigurable ECAs - Part 5 (Student Project #3)
Design How-To  
1/16/2008   Post a comment
In this case study, a student at Virginia Tech (Alexander R. Marschner) compares the task of implementing an image processing algorithm on an FPGA and an ECA.
Low-cost FPGA-based ADC interface reference design
Product News  
1/15/2008   Post a comment
This LatticeECP2/M FPGA Interface to Texas Instruments' ADS6000 ADC family is claimed to delivers exceptional performance and value.
New ESL synthesis and verification flow from Mentor and Calypto
Product News  
1/15/2008   Post a comment
Mentor and Calypto announce an ESL synthesis and verification flow featuring Catapult C Synthesis and the SLEC Sequential Equivalence Checker.
Catapult C and SLEC get integrated flow
Product News  
1/15/2008   Post a comment
Mentor Graphics and Calypto Design Systems Announce Customer-Proven Electronic System Level Synthesis and Verification Flow Featuring Catapult C Synthesis and SLEC Sequential Equivalence Checker.
EDA Outreach
Blog  
1/15/2008   1 comment
An industry that lives on change as the root of progress should be able to see and gather what is needed to increase its visibility.
Utilizing Clock-Gating Efficiency to Reduce Power
Design How-To  
1/15/2008   4 comments
Clock gating can be applied at multiple levels of abstraction, but RTL is the most effective point in the design process. Measuring clock-gating efficiency is an accurate guide to power optimization because it takes into account switching activity. RTL designers can use clock-gating efficiency to pinpoint hotspots and concentrate their optimization efforts.
OCP-IP announces new debug specification
News & Analysis  
1/14/2008   Post a comment
New OCP-IP debug specification supports on-chip system analysis and access to embedded information at the core, multicore, and systems levels.
EDA ekes out modest growth as action moves offshore
News & Analysis  
1/14/2008   Post a comment
The latest statistics from the EDA Consortium show semiconductor and electronic design are continuing their gradual shift outside North America. with modest single-digit growth overall for the sector that supplies chip and system design software.
Page 1 / 2   >   >>


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