IBM calls for modeling standard News & Analysis 1/31/2008 Post a comment The IBM-led Power.org group overseeing the Power CPU architecture is about to start an internal effort to define interface standards to link chip models with simulation tools for cores used in Power CPU-based designs, something the broader industry needs to lower design costs and shorten time-to-market, said and IBM executive.
OneSpin bites back Programmable Logic DesignLine Blog 1/31/2008 Post a comment An email from Aaik van der Poe at Mentor sparks a feisty response from Michael Siegel at OneSpin.
DesignCon probes high-speed signaling issues News & Analysis 1/30/2008 Post a comment As signals move deeper into multi-gigabit territory, engineers are calling for more attention to the rising problems of modeling the interrelated affects of power, signaling and timing, issues that will be debated at next week's DesignCon event.
Viewpoint: Power Format Battles Over Design How-To 1/29/2008 Post a comment Power management for chip design continues to be in the forefront, be it for optimization, analysis or verification. However, the power format battles have subsided and a single IEEE standard appears to be well on track.
Power Integrity and Energy Aware Floor Planning Design How-To 1/29/2008 Post a comment Extreme performance and frequency are no longer dominant design goals for SoC's. Recent years have witnessed changes in microprocessors' architectures, with multi-GHz unicore CPU devices abandoned in favor of low-frequency multi-core variants, and frequency becoming a forgotten memory.
Avnet, ADI and Micron team on video surveillance development kit Product News 1/24/2008 Post a comment The second generation of the Digital Video Surveillance Kit provides a simplified prototype development platform for intelligent video surveillance applications -- combining the unique video handling capabilities of the Blackfin' processor from Analog Devices and state-of-the-art CMOS image sensors from Micron Technology.
Video: Simulator hits 7 billion instructions/s News & Analysis 1/23/2008 Post a comment Embedded Systems Technology Inc. believes it has hit an important milestone in systems simulation software, simulating four cars and their interactions, spanning 98 controllers running 7 billion instructions/second.
Video: startup explores analog EDA problems News & Analysis 1/22/2008 Post a comment Startup Berkeley Design Automation is working on new capabilities to analyze in software analog effects in communications between die in a multi-chip package that can impact device yields, said company founder and chief executive Ravi Subramanian in a video interview with EE Times.
Simulation of Proprietary Low Power Wireless Systems Design How-To 1/17/2008 Post a comment When developing a proprietary short-range device system, it is critical to ensure that the design meets local regulatory requirements as well as design parameters. By using a simulation tool, designers can save time and keep regulations in mind.
Catapult C and SLEC get integrated flow Product News 1/15/2008 Post a comment Mentor Graphics and Calypto Design Systems Announce Customer-Proven Electronic System Level Synthesis and Verification Flow Featuring Catapult C Synthesis and SLEC Sequential Equivalence Checker.
EDA Outreach Blog 1/15/2008 1 comment An industry that lives on change as the root of progress should be able to see and gather what is needed to increase its visibility.
Utilizing Clock-Gating Efficiency to Reduce Power Design How-To 1/15/2008 4 comments Clock gating can be applied at multiple levels of abstraction, but RTL is the most effective point in the design process. Measuring clock-gating efficiency is an accurate guide to power optimization because it takes into account switching activity. RTL designers can use clock-gating efficiency to pinpoint hotspots and concentrate their optimization efforts.
EDA ekes out modest growth as action moves offshore News & Analysis 1/14/2008 Post a comment The latest statistics from the EDA Consortium show semiconductor and electronic design are continuing their gradual shift outside North America. with modest single-digit growth overall for the sector that supplies chip and system design software.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments