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posted in January 2010
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SiliconBlue claims 100 design wins
Programmable Logic DesignLine Blog  
1/30/2010   Post a comment
I recently spoke with Kapil Shankar, CEO of FPGA startup SiliconBlue Technologies, who told me the company now has over 100 design wins under its belt and will seek another round of financing in the next few months.
ASIC pioneer reinvents 3-D FPGAs
Product News  
1/29/2010   8 comments
By building a three-dimensional field-programmable FPGA with an ultra-dense anti-fuse interconnect, NuPGA claims to be able to achieve the density of an ASIC at a fraction of the cost.
Agilent to offer RF small-signal products design kit from NXP
News & Analysis  
1/28/2010   Post a comment
Agilent Technologies Inc., is to offer a NXP Semiconductors' design kit for RF small-signal products within Agilent's Advanced Design System (ADS).
Teklatech joins ARM Connected Community
News & Analysis  
1/27/2010   Post a comment
EDA startup Teklatech A/S (Copenhagen, Denmark), provider of floorplanning and clock distribution network solutions, announced it has joined the ARM Connected Community.
MediaTek deploys EdXact's Jivaro netlist reduction platform for analog circuits
News & Analysis  
1/27/2010   Post a comment
Backend verification specialist, EdXact SA (Grenoble, France) and MediaTek Inc., (Hsin-Chu, Taiwan), a fabless semiconductor company for wireless communications and digital multimedia solutions, have entered a strategic relationship to deploy EdXact's netlist reduction platform for analog circuits.
MegaChips licenses Forte's HLS software
Product News  
1/27/2010   1 comment
Japan-based MegaChips Corp. announced it has adopted Cynthesizer SystemC high-level synthesis (HLS) software from Forte Design Systems for its hardware and electronic system level (ESL) design needs.
Berkeley, Solido claim faster IC variation analysis
Product News  
1/27/2010   Post a comment
EDA companies Berkeley Design Automation Inc. and Solido Design Automation Inc. have validated a flow for rapid reduction in variation risk in nanometer designs at the transistor level.
Altera tops estimates, touts advantage at 40-nm
News & Analysis  
1/26/2010   Post a comment
Programmable logic vendor Altera Corp. Tuesday (Jan. 26) reported sharp increases in fourth quarter 2009 revenue and profit and the company's chief executive predicted that its lead in 40-nm FPGAs would help drive growth in 2010.
Analysts cautious about Xilinx inventory
News & Analysis  
1/26/2010   Post a comment
Wall Street analysts gave programmable logic vendor Xilinx generally high marks on the company's announcement of record quarterly revenue last week, but at least some noted concerns about Xilinx inventory.
Berkeley Design Automation partners Solido Design Automation to accelerate nanometer IC variation analysis
News & Analysis  
1/26/2010   Post a comment
Berkeley Design Automation, Inc., provider of the Analog FastSPICE unified circuit verification platform (AFS Platform), and Solido Design Automation, provider of Variation Designer, have developed a validated flow for rapid reduction in variation risk in nanometer designs at the transistor level.
CoFluent Studio generates SystemC models for Mentor's Questa platform
News & Analysis  
1/26/2010   Post a comment
CoFluent Design said its CoFluent Studio ESL modeling and simulation software environment automatically generates SystemC models and test cases for Mentor Graphics' Questa functional verification platform.
Embedded system virtualization for executable specifications and use case modeling
Design How-To  
1/26/2010   Post a comment
To reduce the time-to-market of embedded system projects, virtual hardware platforms offer a method to develop hardware-dependent software and application software before production hardware is available. However, for true system-level specification and architecture optimization, full-system virtualization is required, including abstract models of HW, behavioral models of application SW and use cases.
MediaTek licenses Edxact's netlist reduction tool
News & Analysis  
1/26/2010   Post a comment
Taiwan chip maker Mediatek Inc. announced it has selected Edxact's Jivaro netlist reduction platform for analog circuits.
LG Electronics licenses EVE's emulation platform
News & Analysis  
1/26/2010   Post a comment
LG Electronics Inc. announced it has selected EVE's ZeBu emulation platform for the verification of its high performance, mass-market consumer products.
Top 10 growth markets for ICs
News & Analysis  
1/25/2010   Post a comment
So what are the top-10 growth categories for 2010?
Apache posts double-digit growth in 2009
News & Analysis  
1/25/2010   Post a comment
Apache Design Solutions Inc. (San Jose, Calif.), a vendor of power and noise analysis EDA software, said it has reported double-digit growth from 2008 to 2009.
Enhanced WEBENCH tool accelerates multi-output DC-DC power supply design
Product News  
1/25/2010   Post a comment
National Semiconductor has introduced WEBENCH Power Architect, a design tool that allows engineers to rapidly create, model and implement multiple-output, high-performance DC-DC power supplies for an entire system.
MIPS appoints former Cavium exec as CEO
News & Analysis  
1/25/2010   Post a comment
Processor intellectual property licensor MIPS Technologies Inc. (Sunnyvale, Calif.) has announced the appointment of Sandeep Vij as president, chief executive officer and director, replacing interim CEO Anthony Holbrook who will continue to serve as chairman.
VC investment fell in 2009, Q4 signals change
News & Analysis  
1/25/2010   Post a comment
Venture capitalists invested $17.7 billion in 2,795 deals in 2009, marking the lowest level of dollar investment since 1997, according to the MoneyTree Report by PricewaterhouseCoopers and the National Venture Capital Association (NVCA), based on data from Thomson Reuters.
NEC Electronics announces the 78K0/Ix2 LED microcontroller demonstration kit
Product News  
1/25/2010   Post a comment
NEC Electronics announces the 78K0/Ix2 LED microcontroller demonstration kit, enabling efficient and intelligent LED driver design without any additional driver ICs but the company's single flexible 78K0/Ix2 MCU.
Design for diagnosis to improve IC yield
Design How-To  
1/25/2010   Post a comment
Although scan diagnosis is an established, automated technique for localizing defects for failure analysis (FA), raising silicon production yield, and assisting first silicon debug, it's often an afterthought and taken for granted.
Effective smartphone accessory design
Design How-To  
1/25/2010   2 comments
Smartphones and MP3 players open up infinite applications and associated opportunities for designers of accessories. The challenges are complex, but through adherence to some basic guidelines, an accessory product can be a game changer for your company.
VLSI pioneer Conway honored with IEEE award
News & Analysis  
1/23/2010   Post a comment
The IEEE Computer Society's Computer Pioneer Award for 2009 has been given to University of Michigan professor Lynn Conway who helped revolutionize Very Large System Integration design.
Applying virtual system integration and test to validate requirements and verify designs
Design How-To  
1/22/2010   Post a comment
Virtual system integration and test using Model-Based Design uncovers errors introduced in the requirements and design phases of embedded system development, well before the physical testing phase.
Early verification cuts design time and cost in algorithm-intensive systems
Design How-To  
1/22/2010   Post a comment
In this article, The MathWorks explains three practical approaches to early verification in order to reduce verification time and improve the performance of the designs.
Three-bit-per-cell NAND products entering main stage
News & Analysis  
1/22/2010   Post a comment
UBM TechInsights has started analyzing the industry-leading three-bit-per-cell manufacturer SanDisk's 43-nm three-bit-per-cell 32-Gb NAND flash found in the SanDisk memory card and the Intel Micron's 32-nm three-bit-per-cell 32-Gb NAND flash.
TI hits home run with Chronos sportswatch wireless dev kit
News & Analysis  
1/21/2010   2 comments
The Texas Instruments product management team knew they were on to something as they prepped for the November '09 launch of the eZ430 Chronos low-power wireless MCU development kit, but they had no idea that within weeks it would surpass the 5,000-unit mark and in doing so leave previous kit-launch records in the dust.
Using compression to meet pin-limited test requirements
Design How-To  
1/21/2010   Post a comment
Timely delivery of highly reliable semiconductor products to market is essential to success in today’s competitive business environment. As if following through on this objective were not already challenging enough, companies today are facing yet another challenge: fewer pins available for digital testing.
Leti, R3Logic create joint lab on 3D integration, packaging
News & Analysis  
1/21/2010   Post a comment
CEA-Leti and R3Logic Inc., a U.S. 3D IC EDA company, have signed a three-year common lab agreement to develop 3D design methodologies for consumer and wireless applications.
Mentor Graphics announces series of talks on low power design
News & Analysis  
1/21/2010   Post a comment
Mentor Graphics announced a new series of Tuesday Tech Talks, focused on low-power design challenges, for electronics engineers.
Xilinx posts record quarterly sales
News & Analysis  
1/20/2010   Post a comment
Programmable logic vendor Xilinx posted record sales in the quarter ended Jan. 2, with the company's top executive crediting in large part sales of its Virtex-5 FPGAs.
Ex-ST exec calls for EDA to take strategic view
News & Analysis  
1/20/2010   Post a comment
When asked if the EDA industry has a roadmap, Joseph Borel, ex-executive vice president in central research and development at STMicroelectronics NV (Switzerland, Geneva), answers affirmatively as Europe continually renews the Medea+ EDA roadmap. The real question should however be: Does the EDA industry need an international roadmap?
Beware of DPA attacks
Programmable Logic DesignLine Blog  
1/20/2010   Post a comment
Benjamin Jun, vice president of technology at Cryptography Research has a message for FPGA users regarding differential power analysis attacks.
Dolphin Integration adds standard cell library
Product News  
1/20/2010   Post a comment
EDA and IP company Dolphin Integration SA announced it has extended its portfolio of standard cell libraries to meet low power designs expectations.
Firm rolls TCP-offload engine SoC IP
Product News  
1/20/2010   Post a comment
IP developer Intelop announced delivery of its second generation TCP offload engine SoC integrated with ARP hardware module, G Bit Ethernet MAC and AMBA 2.0 bus interface running at 2 Gbps sustained rates.
Verilog simulator claims 30% faster speed
Product News  
1/20/2010   Post a comment
SynaptiCAD released the first 64-bit Linux version of VeriLogger Extreme, a Verilog simulation and debug environment.
How to efficiently use long record analysis to debug signals
Design How-To  
1/20/2010   1 comment
Engineers need the ability to acquire and analyze very long time windows with 20 million points or more to identify the source of problems. Similarly long record capture and analysis is required in spread spectrum clocking (SSC) applications used to reduce EMI emissions.
Firm uses Impulse C to create passenger-counting chip
Product News  
1/20/2010   Post a comment
Impulse Accelerated Technologies announced last week that Hella Aglaia Mobile Vision has completed a design for a computer vision 3-D automatic passenger counting system using Impulse tools and Xilinx FPGAs in an ASIC prototyping flow.
Samsung to pay $900 million in Rambus license deal
News & Analysis  
1/19/2010   Post a comment
South Korea's Samsung Electronics will pay about $900 million over five years to license technology from Rambus under the terms an agreement that settles all litigation between the two companies.
TSMC qualifies Atoptech's physical design tool on 40nm process
Product News  
1/19/2010   Post a comment
IC physical design startup Atoptech Inc. announced its Aprisa physical design solution has been qualified for TSMC's 40nm technology node.
EDA from "soft business to competitive business"
News & Analysis  
1/19/2010   Post a comment
According to Joseph Borel, JB-R&D EDA consulting company, the European EDA roadmapping experience could help build the framework of the International EDA roadmap provided that the EDA vendor community is ready to jump in the bandwagon...
Azuro reports growth in 2009
News & Analysis  
1/19/2010   Post a comment
Power-focused EDA startup Azuro Inc. (Santa Clara, Calif.) announced it has closed its fifth consecutive year of revenue growth.
Study gives mixed marks to high-level synthesis
News & Analysis  
1/18/2010   2 comments
High-level synthesis tools for FPGA design deliver excellent results and are very usable, but do not fully abstract users from the FPGA RTL flow, according to a study conducted by benchmarking and analysis firm BDTI.
Xilinx to go with TSMC at 28-nm, says analyst
News & Analysis  
1/15/2010   Post a comment
Market-leading programmable logic vendor Xilinx is set to use TSMC for foundry services at the 28-nm node, according to one analyst.
SOFTWARE TOOLS - Embedded virtualization software supports new Intel Core Embedded Processors
Product News  
1/15/2010   Post a comment
TenAsys Corporation's embedded virtualization software supports new Intel Core embedded processors, giving INtime RTOS more platform choices.
Nexus teardown, CES and Intel-FPGA tale, lead weekly story ranking
Blog  
1/15/2010   Post a comment
Here are the top five online stories for the week beginning Sunday, Jan. 10, as ranked by EE Times readers, up to and including Friday, Jan. 15. The ranking is based on the number of reader "views" or "hits" on a particular article.
Computer Simulation Technology now ships version 2010 of its CST Studio Suite
Product News  
1/15/2010   Post a comment
Designed to solve electromagnetic problems, the CST Studio Suite version 2010 comes with an extended range of solvers, offering different solution options within one design environment. CST Microwave Studio now incorporates an asymptotic solver.
Efficient interfacing with external memory in high-end video
News & Analysis  
1/15/2010   Post a comment
The bandwidth required for different processing engines can vary dramatically depending on the image content and processing algorithms used. A careful analysis of all individual bandwidth requirements, their access pattern and latency requirement is very crucial in order to select the external memory and architect the DDR controller and decide the system arbitration mechanism. In this article, different aspects of DDR controller and DDR/DDR2 memory module and different operational trade-offs are
Mentor speeds USB 2.0 products verification
Product News  
1/14/2010   Post a comment
Mentor Graphics Corp. announced the availability of a hardware-assisted tool that accelerates the verification of USB. 2.0 products.
EDA revenue grew sequentially in Q309, says EDAC
News & Analysis  
1/14/2010   1 comment
EDA revenue improved on a sequential basis in the third quarter of 2009, ending the longest string of successive declines since at least 1997, according to the EDA Consortium trade group.
Page 1 / 2   >   >>


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