SiliconBlue claims 100 design wins Programmable Logic DesignLine Blog 1/30/2010 Post a comment I recently spoke with Kapil Shankar, CEO of FPGA startup SiliconBlue Technologies, who told me the company now has over 100 design wins under its belt and will seek another round of financing in the next few months.
ASIC pioneer reinvents 3-D FPGAs Product News 1/29/2010 8 comments By building a three-dimensional field-programmable FPGA with an ultra-dense anti-fuse interconnect, NuPGA claims to be able to achieve the density of an ASIC at a fraction of the cost.
MegaChips licenses Forte's HLS software Product News 1/27/2010 1 comment Japan-based MegaChips Corp. announced it has adopted Cynthesizer SystemC high-level synthesis (HLS) software from Forte Design Systems for its hardware and electronic system level (ESL) design needs.
Altera tops estimates, touts advantage at 40-nm News & Analysis 1/26/2010 Post a comment Programmable logic vendor Altera Corp. Tuesday (Jan. 26) reported sharp increases in fourth quarter 2009 revenue and profit and the company's chief executive predicted that its lead in 40-nm FPGAs would help drive growth in 2010.
Analysts cautious about Xilinx inventory News & Analysis 1/26/2010 Post a comment Wall Street analysts gave programmable logic vendor Xilinx generally high marks on the company's announcement of record quarterly revenue last week, but at least some noted concerns about Xilinx inventory.
Embedded system virtualization for executable specifications and use case modeling Design How-To 1/26/2010 Post a comment To reduce the time-to-market of embedded system projects, virtual hardware platforms offer a method to develop hardware-dependent software and application software before production hardware is available. However, for true system-level specification and architecture optimization, full-system virtualization is required, including abstract models of HW, behavioral models of application SW and use cases.
MIPS appoints former Cavium exec as CEO News & Analysis 1/25/2010 Post a comment Processor intellectual property licensor MIPS Technologies Inc. (Sunnyvale, Calif.) has announced the appointment of Sandeep Vij as president, chief executive officer and director, replacing interim CEO Anthony Holbrook who will continue to serve as chairman.
VC investment fell in 2009, Q4 signals change News & Analysis 1/25/2010 Post a comment Venture capitalists invested $17.7 billion in 2,795 deals in 2009, marking the lowest level of dollar investment since 1997, according to the MoneyTree Report by PricewaterhouseCoopers and the National Venture Capital Association (NVCA), based on data from Thomson Reuters.
Design for diagnosis to improve IC yield Design How-To 1/25/2010 Post a comment
Although scan diagnosis is an established, automated technique for localizing defects for failure analysis (FA), raising silicon production yield, and assisting first silicon debug, it's often an afterthought and taken for granted.
Effective smartphone accessory design Design How-To 1/25/2010 2 comments Smartphones and MP3 players open up infinite applications and associated opportunities for designers of accessories. The challenges are complex, but through adherence to some basic guidelines, an accessory product can be a game changer for your company.
Three-bit-per-cell NAND products entering main stage News & Analysis 1/22/2010 Post a comment UBM TechInsights has started analyzing the industry-leading three-bit-per-cell manufacturer SanDisk's 43-nm three-bit-per-cell 32-Gb NAND flash found in the SanDisk memory card and the Intel Micron's 32-nm three-bit-per-cell 32-Gb NAND flash.
TI hits home run with Chronos sportswatch wireless dev kit News & Analysis 1/21/2010 2 comments The Texas Instruments product management team knew they were on to something as they prepped for the November '09 launch of the eZ430 Chronos low-power wireless MCU development kit, but they had no idea that within weeks it would surpass the 5,000-unit mark and in doing so leave previous kit-launch records in the dust.
Using compression to meet pin-limited test requirements Design How-To 1/21/2010 Post a comment Timely delivery of highly reliable semiconductor products to market is essential to success in today’s competitive business environment. As if following through on this objective were not already challenging enough, companies today are facing yet another challenge: fewer pins available for digital testing.
Ex-ST exec calls for EDA to take strategic view News & Analysis 1/20/2010 Post a comment When asked if the EDA industry has a roadmap, Joseph Borel, ex-executive vice president in central research and development at STMicroelectronics NV (Switzerland, Geneva), answers affirmatively as Europe continually renews the Medea+ EDA roadmap. The real question should however be: Does the EDA industry need an international roadmap?
Beware of DPA attacks Programmable Logic DesignLine Blog 1/20/2010 Post a comment Benjamin Jun, vice president of technology at Cryptography Research has a message for FPGA users regarding differential power analysis attacks.
Firm rolls TCP-offload engine SoC IP Product News 1/20/2010 Post a comment IP developer Intelop announced delivery of its second generation TCP offload engine SoC integrated with ARP hardware module, G Bit Ethernet MAC and AMBA 2.0 bus interface running at 2 Gbps sustained rates.
How to efficiently use long record analysis to debug signals Design How-To 1/20/2010 1 comment Engineers need the ability to acquire and analyze very long time windows with 20 million points or more to identify the source of problems. Similarly long record capture and analysis is required in spread spectrum clocking (SSC) applications used to reduce EMI emissions.
EDA from "soft business to competitive business" News & Analysis 1/19/2010 Post a comment According to Joseph Borel, JB-R&D EDA consulting company, the European EDA roadmapping experience could help build the framework of the International EDA roadmap provided that the EDA vendor community is ready to jump in the bandwagon...
Study gives mixed marks to high-level synthesis News & Analysis 1/18/2010 2 comments High-level synthesis tools for FPGA design deliver excellent results and are very usable, but do not fully abstract users from the FPGA RTL flow, according to a study conducted by benchmarking and analysis firm BDTI.
Efficient interfacing with external memory in high-end video News & Analysis 1/15/2010 Post a comment The bandwidth required for different processing engines can vary dramatically depending on the image content and processing algorithms used. A careful analysis of all individual bandwidth requirements, their access pattern and latency requirement is very crucial in order to select the external memory and architect the DDR controller and decide the system arbitration mechanism.
In this article, different aspects of DDR controller and DDR/DDR2 memory module and different operational trade-offs are
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments