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Content tagged with Design Tools (EDA)
posted in January 2011
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Which elements form a human body?
Blog  
1/31/2011   11 comments
Have you ever wondered how many elements there are in a human body? Would you be surprised to hear that today’s integrated circuits are more complicated (element-wise) than we are?
Xilinx experts have lots to say at DesignCon 2011
News & Analysis  
1/31/2011   1 comment
Through silicon vias (TSVs), signal integrity, design methodologies, FPGA-based SoC development, demonstrations, technical sessions, the future of FPGAs, and more...
AutoESL acquisition a great move for Xilinx
Blog  
1/31/2011   1 comment
In a move that makes a lot of sense, the folks at Xilinx have just announced the acquisition of the high level synthesis company AutoESL Design Technologies.
Synopsys: IC Compiler speeds DRC up to 7X
News & Analysis  
1/31/2011   Post a comment
Synopsys released the latest version of its Galaxy Implementation Platform and IC Compiler, including enhancements that the company claims make automatic design rule check repair up to 7 times faster.
Cadence rolls 28-nm digital design flow
News & Analysis  
1/31/2011   Post a comment
EDA vendor Cadence Design Systems rolled out an end-to-end digital design flow for 28-nm based on the company's Encounter platform.
Optiphase creates waveform and timing generator instrument using Opal Kelly XEM3001 FPGA module
News & Analysis  
1/31/2011   1 comment
Optiphase has created a PC-controlled Waveform and Timing Generator (WTG) instrument using the Opal Kelly XEM3001 FPGA module mated with a custom adapter PCB.
Creating a PC-controlled, FPGA-based waveform and timing generator (WTG)
Design How-To  
1/31/2011   12 comments
This Product How-To article describes how a PC-controlled Waveform and Timing Generator (WTG) Instrument was developed using the Opal Kelly XEM3001 FPGA-USB module mated with an Optiphase custom adapter PCB.
Apache releases CPM v2.0 at DesignCon
Product News  
1/31/2011   Post a comment
At DesignCon here Apache Design Solutions released CPM v2.0, its next generation Chip Power Model (CPM) intended for co-analysis/co-optimization of the chip, package, and system.
Blue Pearl rolls tool suite with native visual verification environment
Product News  
1/28/2011   Post a comment
Blue Pearl Software Inc. (Santa Clara, Calif.) is proposing a transformative approach with the introduction of its Blue Pearl Suite for automating design analysis, CDC (clock domain crossing) checking, SDC (Synopsys Design Constraints) creation, visualization and validation.
Magillem rolls Checker Suite, Compliance Lab conform with IP-XACT/IEEE 1685
Product News  
1/28/2011   Post a comment
Magillem SA (Paris, France) is promoting IP Reuse and interoperability through IEEE 1685 with the introduction of the IP-XACT Checker Suite Software and Compliance Lab Services.
Video: Two girls in a very small box
Blog  
1/27/2011   7 comments
We’ve all see contortionists doing the most amazing things … well this is more amazing than most…
7 myths of analog and mixed-signal ASIC design
Design How-To  
1/27/2011   15 comments
Frostholm aims to help readers select the best partner for their analog and mixed-signal ASIC design.
Introducing Opal Kelly’s new entry-Level Xilinx Spartan-6 USB FPGA module – the XEM6001
Product News  
1/27/2011   4 comments
This XEM6001 module is offered as an upgrade to Opal Kelly’s popular XEM3001, providing many enhancements, while keeping the same footprint and pinout.
Do you keep a ‘to-do’ list?
Blog  
1/27/2011   5 comments
I was just chatting to someone about the way in which I keep lists of ‘things to do’ and I thought I’d check to see how many of you do the same.
New open-source toolchain facilitates configurable IP core packaging
Blog  
1/27/2011   1 comment
CoreTML framework is both open-source and vendor-neutral. The cores in question are basically RTL templates and therefore can be used both for FPGA and ASIC projects.
EVE enhances ZeBu debugging capabilities
Product News  
1/27/2011   Post a comment
EVE SA (Palaiseau, France) has developed superior debugging capabilities for its ZeBu emulation platform so that designers can quickly and easily generate design waveforms.
EDA firm Calypto names new CEO
News & Analysis  
1/27/2011   Post a comment
Privately held EDA vendor Calypto Design Systems announced that Doug Aitelli, currently the company's current vice president of worldwide sales, would assume the position of CEO.
Turbo-Boost MATLAB-Simulink with a RocketDrive!
Blog  
1/26/2011   2 comments
Now, MATLAB-Simulink, RocketDrive, and RocketVision can be used in conjunction with each other to significantly speed the entire design-debug-verification flow.
Synopsys launches DesignWare DDR PHY compiler
Product News  
1/26/2011   Post a comment
Synopsys Inc. has introduced the DesignWare DDR PHY compiler to facilitate the integration of memory interface IP.
How to instrument your design with simple SystemVerilog assertions
Design How-To  
1/26/2011   3 comments
Functional coverage, stimulus generation, and run management are the three major tasks of today’s functional verification environment. Functional coverage arguably looms as the most important, largely because coverage closure is the main criteria for tapeout. When using an assertion-based coverage methodology, designers must consider not only how to capture assertions, but more importantly, which assertions and coverage points to capture and whether enough have been captured. Understanding “asse
Docea Power joins Synopsys System-Level Catalyst Program
News & Analysis  
1/26/2011   Post a comment
Design-for-power startup company Docea Power SAS (Moirans, France) said it has joined the Synopsys System-Level Catalyst Program to guarantee the interoperability of its Aceplorer software tool with Synopsys system-level solutions.
Signal processing company looking for a product – any ideas?
Blog  
1/25/2011   4 comments
Hmmm, I just heard from the folks at company with vast expertise in signal processing who are looking for a killer product to develop, and they’re asking for our thoughts…
Another high-level synthesis company targeting FPGAs
Blog  
1/25/2011   4 comments
I had predicted that we would see more consolidation this year, but had not expected to see new entrants…
R&D predictability: The path to profitability
Blog  
1/25/2011   7 comments
Poor schedule predictability of IC development projects is often blamed on unforeseeable events, but this picture is incomplete and inaccurate.
Altera unveils 28-nm FPGA portfolio with a few surprises
Product News  
1/25/2011   1 comment
The folks at Altera are taking a very different approach to their forthcoming 28 nm FPGA portfolio as compared to their arch-rivals at Xilinx.
Video: Mirror, mirror on the wall...
Blog  
1/24/2011   5 comments
I just saw a really funny ‘spoof’ video involving a fake mirror…
Zoran uses EVE's ZeBu for multi-function peripheral chip designs
News & Analysis  
1/24/2011   Post a comment
Digital TV semiconductor supplier Zoran Corp. said it has deployed EVE's ZeBu emulation platform for the verification of its high-performance, multi-function peripheral SoC designs.
Equity firm buys EDA startup OneSpin
News & Analysis  
1/24/2011   Post a comment
UK based private equity firm Azini Capital acquired German EDA startup OneSpin Solutions from founding investors Apax Partners and Infineon.
Standard issued for PCB IP protection
News & Analysis  
1/24/2011   1 comment
IPC, the industry association that looks after interests of companies involved in electronics interconnection, has released IPC-1071, a standard on printed circuit board intellectual property protection.
No room for error: Creating highly reliable, high-availability FPGA designs
Blog  
1/23/2011   3 comments
Designers of FPGAs for military and aerospace applications need to increase the reliability and availability of their designs. This whitepaper explains all.
Free I/O: Improving FPGA clock distribution control
Design How-To  
1/23/2011   4 comments
This article examines offers practical advice for designers who are considering ways to enable additional FPGA I/O, or improve clock network performance.
Elliptic launches security processing engine for 4G wireless markets
Product News  
1/21/2011   Post a comment
The CLP-620 Security Protocol Accelerator - LTE (SPAcc-LTE) from Elliptic Technologies is a high-performance cost- and power-efficient security engine for the developing 4th Generation mobile wireless markets. CLP-620 is the first security IP on the market that supports all algorithms required for 4G wireless markets around the world, including the ZUC based algorithms which have been recently introduced to target wireless networks in key Asian markets.
Tradeoff: Dynamic range and bandwidth in signal analysis
Design How-To  
1/21/2011   9 comments
Examining the tradeoff between dynamic range and bandwidth in signal analysis.
Spreadtrum tapes out 40-nm LP chip using Cadence Silicon Realization
News & Analysis  
1/21/2011   Post a comment
Subject to time-to-market factors, Spreadtrum Communications Ltd. (Shanghai, China) has adopted Cadence's Silicon Realization products for the design of a 40nm low power TD-HSPA/TD-SCDMA multi-mode communication baseband processor. The chip was taped out with one-pass silicon success and is commercially available in China.
Periodic Tables (there are more ways to skin a cat…)
Blog  
1/21/2011   11 comments
To be honest, I hadn’t realized just how many variations of these little rascals there are. Even the standard one we all grew up with at high school comes in so many flavors that it makes your eyes water.
Global Warming – Fact or Fiction?
Blog  
1/20/2011   14 comments
On the one hand I have an un-reasoned, un-researched believe that Global Warming is real and is happening now .. on the other hand...
Analog Bits preps PLL IP for Common Platform 28nm LP process
Product News  
1/20/2011   Post a comment
Analog Bits Inc. has introduced a design kit for Phase-Locked Loop (PLL) IP products, supporting the Common Platform 28nm process technology.
Mentor achieves test chip for Common Platform 32/28nm technologies
Product News  
1/20/2011   Post a comment
As part of a collaboration with the Common Platform Alliance (CPA), Mentor Graphics Corp. has designed a test chip using its netlist-to-GDSII solution for CPA 32nm and 28nm high-k metal gate IC manufacturing technologies.
Managing coverage grading in complex multicore microprocessor environments
Design How-To  
1/19/2011   Post a comment
Verification of a multicore design is substantially more complex than a single core design. It involves the execution of tens of thousands of tests in a typical regression. As this regression can take a week or more to execute, there is a need for designers to have available a highly optimized test list that maximizes line and toggle coverage. This article describes a customized coverage grading solution, co-developed by AMD and Synopsys, which has saved AMD several months of run time by providi
Carbon posts 35% growth in 2010
News & Analysis  
1/19/2011   5 comments
EDA tool vendor Carbon Design Systems said it has closed calendar year 2010 with a 35-percent year-over-year growth as it strengthens its position in the virtual platform market.
Linc Jepson's 74ze leverages Russian and American engineering talent to persevere
The Entrepreneurial Engineer  
1/18/2011   Post a comment
Sean Murphy sits down with entrepreneur Linc Jepson.
Amazing, thought-provoking, and laugh-out-loud videos
Blog  
1/18/2011   2 comments
Here are some videos and other things – some will give you pause to ponder and others will make you laugh out loud…
How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Design How-To  
1/18/2011   61 comments
All-Digital Digital-to-Analog Converters (DACs) offer 50% lower power, 68% smaller area, process technology independence, reduced risk and cycle time, digital integration and synthesis, and easier radiation-hardened design.
Tokyo University uses Docea's Aceplorer for NVM design
News & Analysis  
1/18/2011   Post a comment
Design-for-power startup company Docea Power SAS (Moirans, France) announced that the University of Tokyo has licensed its Aceplorer software to design non-volatile memory (NVM) architecture as part of a Japanese research project.
Very cool FPGA-based graphics controller
Product News  
1/15/2011   1 comment
This FPGA-based control module involves an integration of three controllers (SVGA, SDRAM, and FLASH), thereby providing additional functionality to any embedded system.
Designing an FPGA-based graphics controller
Design How-To  
1/15/2011   7 comments
This FPGA-based control module involves an integration of three controllers (SVGA, SDRAM, and FLASH), thereby providing additional functionality to any embedded system.
Book Review: A Short History of Nearly Everything by Bill Bryson
Engineer’s Bookshelf  
1/15/2011   2 comments
As a follow-on to my recent review on Bill Bryson’s latest book – 'At Home: A Short History of Private Life' – there’s another Bryson book that I particularly enjoy called 'A Short History of Nearly Everything'.
EU project progresses in regularity-aware synthesis methodology development
News & Analysis  
1/14/2011   Post a comment
After one year of operation, the EU-funded Synaptic (SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms) project has demonstrated tangible advances in regularity.
Mentor's VP joins ISQED board
News & Analysis  
1/13/2011   Post a comment
The International Society for Quality Electronic Design (ISQED) announced that Joseph Sawicki, vice president and general manager of the Design-to-Silicon division of Mentor Graphics Corp. has joined the group's Strategic Steering Committee.
GlobalFoundries opens for 28-nm business
News & Analysis  
1/13/2011   5 comments
GlobalFoundries Inc., along with EDA and IP partners, has announced the availability of a proven digital design flow for its 28-nm CMOS manufacturing process.
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21 comments
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