Which elements form a human body? Blog 1/31/2011 11 comments Have you ever wondered how many elements there are in a human body? Would you be surprised to hear that today’s integrated circuits are more complicated (element-wise) than we are?
Synopsys: IC Compiler speeds DRC up to 7X News & Analysis 1/31/2011 Post a comment Synopsys released the latest version of its Galaxy Implementation Platform and IC Compiler, including enhancements that the company claims make automatic design rule check repair up to 7 times faster.
EDA firm Calypto names new CEO News & Analysis 1/27/2011 Post a comment Privately held EDA vendor Calypto Design Systems announced that Doug Aitelli, currently the company's current vice president of worldwide sales, would assume the position of CEO.
How to instrument your design with simple SystemVerilog assertions Design How-To 1/26/2011 3 comments Functional coverage, stimulus generation, and run management are the three major tasks of today’s functional verification environment. Functional coverage arguably looms as the most important, largely because coverage closure is the main criteria for tapeout. When using an assertion-based coverage methodology, designers must consider not only how to capture assertions, but more importantly, which assertions and coverage points to capture and whether enough have been captured. Understanding “asse
Standard issued for PCB IP protection News & Analysis 1/24/2011 1 comment IPC, the industry association that looks after interests of companies involved in electronics interconnection, has released IPC-1071, a standard on printed circuit board intellectual property protection.
Elliptic launches security processing engine for 4G wireless markets Product News 1/21/2011 Post a comment The CLP-620 Security Protocol Accelerator - LTE (SPAcc-LTE) from Elliptic Technologies is a high-performance cost- and power-efficient security engine for the developing 4th Generation mobile wireless markets. CLP-620 is the first security IP on the market that supports all algorithms required for 4G wireless markets around the world, including the ZUC based algorithms which have been recently introduced to target wireless networks in key Asian markets.
Spreadtrum tapes out 40-nm LP chip using Cadence Silicon Realization News & Analysis 1/21/2011 Post a comment Subject to time-to-market factors, Spreadtrum Communications Ltd. (Shanghai, China) has adopted Cadence's Silicon Realization products for the design of a 40nm low power TD-HSPA/TD-SCDMA multi-mode communication baseband processor. The chip was taped out with one-pass silicon success and is commercially available in China.
Managing coverage grading in complex multicore microprocessor environments Design How-To 1/19/2011 Post a comment Verification of a multicore design is substantially more complex than a single core design. It involves the execution of tens of thousands of tests in a typical regression. As this regression can take a week or more to execute, there is a need for designers to have available a highly optimized test list that maximizes line and toggle coverage. This article describes a customized coverage grading solution, co-developed by AMD and Synopsys, which has saved AMD several months of run time by providi
Carbon posts 35% growth in 2010 News & Analysis 1/19/2011 5 comments EDA tool vendor Carbon Design Systems said it has closed calendar year 2010 with a 35-percent year-over-year growth as it strengthens its position in the virtual platform market.
Mentor's VP joins ISQED board News & Analysis 1/13/2011 Post a comment The International Society for Quality Electronic Design (ISQED) announced that Joseph Sawicki, vice president and general manager of the Design-to-Silicon division of Mentor Graphics Corp. has joined the group's Strategic Steering Committee.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...