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Content tagged with Design Tools (EDA)
posted in October 2003
Play it again with 'replayable' floorplans
News & Analysis  
10/31/2003   Post a comment
Replayable, or reusable, floorplans can save weeks of design time by letting designers manage floorplan complexity and cope with design changes. Sharlene Gee, applications engineer at ReShape, shows how you can create and use replayable floorplans in this feature article.
French EDA startup is 'fluent' in co-design
News & Analysis  
10/31/2003   Post a comment
Startup CoFluent Design is gearing up to sell a functional and architectural design tool that helps define a hardware/software architecture and can generate C code and synthesizable VHDL.
French EDA startup is 'fluent' in co-design
Product News  
10/31/2003   Post a comment
Startup CoFluent Design is gearing up to sell a functional and architectural design tool that helps define a hardware/software architecture and can generate C code and synthesizable VHDL.
Analyst downgrades EDA sector
News & Analysis  
10/29/2003   Post a comment
Despite remaining bullish about a broad-based recovery of the electronics industry, American Technology Research (ATR) financial analyst Erach Desai is bearish on the entire EDA sector. In a desknote issued Wednesday (Oct. 29), Desai, who covers EDA and semiconductors for ATR, downgraded Synopsys and dropped coverage of two smaller, public EDA firms, Nassda and Verisity. Mike Santarini reports.
National Instruments Enhances Design and Simulation Software
Product News  
10/29/2003   Post a comment
National Instruments announces a product called MATRIXx 6.3. Priced at just under $1700 a pop, it's billed as the company's first release of the control design and simulation software suite it acquired back in January. With updates and enhancements, it's also an initial step in National Instruments long-term plan for MATRIXx support.
Structured ASICs allow improved design flow
News & Analysis  
10/24/2003   Post a comment
Structured ASICs are emerging as a new alternative for mid-volume applications. In this article, Synplicity's John Gallagher shows why you should consider them, and discusses the tooling necessary to support them.
Architecture-based vs. flow-based approach to DFT
Design How-To  
10/24/2003   Post a comment
Increases in the average gate count of ASIC designs is forcing design teams to spend 20 percent to 50 percent of their ASIC development effort on test-related concerns to achieve good test coverage.
Source-synchronous clocks pose challenges
News & Analysis  
10/24/2003   Post a comment
As system-on-chip (SoC) devices are called upon to perform more computation-intensive functions, the amount of data, and the speed with which that data must be moved to and from peripheral devices, is increasing rapidly and pushing the uppermost bounds of performance.
Vectorless test: best bet for high-speed I/O
Design How-To  
10/24/2003   Post a comment
High-volume manufacturers must wrestle with the conundrum of how to cost-effectively test multiple multilane high-speed I/O interfaces-such as PCI Express, HyperTransport and Infiniband-embedded into huge digital system-on-chip designs.
Open architecture ATE tackles test woes
News & Analysis  
10/24/2003   Post a comment
System-on-chip (SoC) testing presents unparalleled challenges that require a fundamental change in thinking for both IC manufacturers and tester makers.
Scan-based transition-fault test can do job
Design How-To  
10/24/2003   Post a comment
Delay-inducing defects are causing increasing concern in the semiconductor industry today, particularly at the leading-edge 130- and 90- nanometer nodes.
Serial storage SoCs demanding to test
News & Analysis  
10/24/2003   Post a comment
The storage industry this year began widespread implementation of serial-based technologies to replace parallel physical-interface standards (AT bus attachment, or ATA, and Small Computer Systems Interface, or SCSI) currently used to connect a system bus to disk storage devices.
Lost Link Bandwidth " How to get it Back
News & Analysis  
10/21/2003   Post a comment
Link bandwidth can be a slippery animal, writes TriCN's John Ellis, in this article adopted from the recent Comms Design Conferent. Without careful thought on the front end of the design, he says, attenuation, reflections and system noise can quickly turn a planned 10 Gbits/s link into mush. A thoughtful approach to the entire signal path " chips to leadframes, leadframes to boards, boards to connectors, connectors to backplanes, and back again " and inclusion of well-chosen equalization techniq
Mentor courts pc-board designers
News & Analysis  
10/20/2003   Post a comment
SystemVerilog assertions unify design and verification
News & Analysis  
10/17/2003   Post a comment
SystemVerilog brings together design, verification, and assertions. In this detailed tutorial, Synopsys' Tom Fitzpatrick explains how SystemVerilog assertions work, examining concurrent assertions, sequential expressions, properties, procedural assertions, and interaction with testbenches.
Arrow, National implement PIPs series
News & Analysis  
10/16/2003   Post a comment
Measurements and Limits of Conducted EMI
News & Analysis  
10/15/2003   Post a comment
In part 2 of this extended series on EMI effects, National Semiconductor's Sanjaya Maniktala takes up the basic concepts of common mode and differential mode noise, the regulatory conducted emission limits, and the related measuring techniques.
Analog vet revamps circuit simulation
News & Analysis  
10/13/2003   Post a comment
ODA Central Library Reference Guide: Symbols
News & Analysis  
10/13/2003   Post a comment
This reference guide details the differences between the ODA Master Library and the standard Mentor Central Library. Several procedures for using the ODA Master Library are explained, including setup, schematic symbols, cells (PCB footprints) including padstacks, and PDBs. The use of symbols in the library is explained, as are symbol partitions and symbol naming conventions. Detailed information on creating symbols is provided, and instructions for editing existing symbols are provided.
EDA vendor enters embedded market with co-development tool
News & Analysis  
10/10/2003   Post a comment
Designed for use with platform FPGAs, the CoVer hardware-software development environment supports parallel design, debug, and test.
A methodology for minimizing leakage current
Design How-To  
10/10/2003   Post a comment
Static leakage current poses a huge problem for sub-100nm ICs. In2Fab's Keith Sabine explains a methodology that selects the best combination of low and high threshold gates to manage performance/power tradeoffs.
Silvaco buys EDA pioneer Simucad
News & Analysis  
10/8/2003   Post a comment
VC Watch
News & Analysis  
10/5/2003   Post a comment
What's catching the attention of venture capitalists these days? Try wireless, FPGAs, and design-for-manufacturing, as TelASIC, Anadigm, and Sigma-C announced VC funding last week.
Jeda language simplifies hardware verification
News & Analysis  
10/3/2003   Post a comment
Jeda is a new hardware verification language (HVL) that claims ease of use, flexibility, and power. In this first public tutorial, Jeda author Atsushi Kasuya and co-authors show how Jeda would be used to construct a hardware model and a testbench for a 4x4 crossbar switch.


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The USB Keys in the Urinal
Terry Cutler, CTO, Digital Locksmiths
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Security is a major obsession today, particularly as the industry makes the shift from traditional, standalone devices to the design of connected, networked systems that are “always ...

Engineer's Bookshelf
Caleb Kraft

The Martian: A Delightful Exploration of Math, Mars & Feces
Caleb Kraft
6 comments
To say that Andy Weir's The Martian is an exploration of math, Mars, and feces is a slight simplification. I doubt that the author would have any complaints, though.

Design Contests & Competitions
Caleb Kraft

Join The Balancing Act With April's Caption Contest
Caleb Kraft
58 comments
Sometimes it can feel like you're really performing in the big tent when presenting your hardware. This month's caption contest exemplifies this wonderfully.

Engineering Investigations
Caleb Kraft

Frankenstein's Fix: The Winners Announced!
Caleb Kraft
8 comments
The Frankenstein's Fix contest for the Tektronix Scope has finally officially come to an end. We had an incredibly amusing live chat earlier today to announce the winners. However, we ...

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