Play it again with 'replayable' floorplans News & Analysis 10/31/2003 Post a comment Replayable, or reusable, floorplans can save weeks of design time by letting designers manage floorplan complexity and cope with design changes. Sharlene Gee, applications engineer at ReShape, shows how you can create and use replayable floorplans in this feature article.
Analyst downgrades EDA sector News & Analysis 10/29/2003 Post a comment Despite remaining bullish about a broad-based recovery of the electronics industry, American Technology Research (ATR) financial analyst Erach Desai is bearish on the entire EDA sector.
In a desknote issued Wednesday (Oct. 29), Desai, who covers EDA and semiconductors for ATR, downgraded Synopsys and dropped coverage of two smaller, public EDA firms, Nassda and Verisity. Mike Santarini reports.
National Instruments Enhances Design and Simulation Software Product News 10/29/2003 Post a comment National Instruments announces a product called MATRIXx 6.3. Priced at just under $1700 a pop, it's billed as the company's first release of the control design and simulation software suite it acquired back in January. With updates and enhancements, it's also an initial step in National Instruments long-term plan for MATRIXx support.
Structured ASICs allow improved design flow News & Analysis 10/24/2003 Post a comment Structured ASICs are emerging as a new alternative for mid-volume applications. In this article, Synplicity's John Gallagher shows why you should consider them, and discusses the tooling necessary to support them.
Source-synchronous clocks pose challenges News & Analysis 10/24/2003 Post a comment As system-on-chip (SoC) devices are called upon to perform more computation-intensive functions, the amount of data, and the speed with which that data must be moved to and from peripheral devices, is increasing rapidly and pushing the uppermost bounds of performance.
Vectorless test: best bet for high-speed I/O Design How-To 10/24/2003 Post a comment High-volume manufacturers must wrestle with the conundrum of how to cost-effectively test multiple multilane high-speed I/O interfaces-such as PCI Express, HyperTransport and Infiniband-embedded into huge digital system-on-chip designs.
Serial storage SoCs demanding to test News & Analysis 10/24/2003 Post a comment The storage industry this year began widespread implementation of serial-based technologies to replace parallel physical-interface standards (AT bus attachment, or ATA, and Small Computer Systems Interface, or SCSI) currently used to connect a system bus to disk storage devices.
Lost Link Bandwidth " How to get it Back News & Analysis 10/21/2003 Post a comment Link bandwidth can be a slippery animal, writes TriCN's John Ellis, in this article adopted from the recent Comms Design Conferent. Without careful thought on the front end of the design, he says, attenuation, reflections and system noise can quickly turn a planned 10 Gbits/s link into mush. A thoughtful approach to the entire signal path " chips to leadframes, leadframes to boards, boards to connectors, connectors to backplanes, and back again " and inclusion of well-chosen equalization techniq
SystemVerilog assertions unify design and verification News & Analysis 10/17/2003 Post a comment SystemVerilog brings together design, verification, and assertions. In this detailed tutorial, Synopsys' Tom Fitzpatrick explains how SystemVerilog assertions work, examining concurrent assertions, sequential expressions, properties, procedural assertions, and interaction with testbenches.
Measurements and Limits of Conducted EMI News & Analysis 10/15/2003 Post a comment In part 2 of this extended series on EMI effects, National Semiconductor's Sanjaya Maniktala takes up the basic concepts of common mode and differential mode noise, the regulatory conducted emission limits, and the related measuring techniques.
ODA Central Library Reference Guide: Symbols News & Analysis 10/13/2003 Post a comment This reference guide details the differences between the ODA Master Library and the standard Mentor Central Library. Several procedures for using the ODA Master Library are explained, including setup, schematic symbols, cells (PCB footprints) including padstacks, and PDBs. The use of symbols in the library is explained, as are symbol partitions and symbol naming conventions. Detailed information on creating symbols is provided, and instructions for editing existing symbols are provided.
A methodology for minimizing leakage current Design How-To 10/10/2003 Post a comment Static leakage current poses a huge problem for sub-100nm ICs. In2Fab's Keith Sabine explains a methodology that selects the best combination of low and high threshold gates to manage performance/power tradeoffs.
VC Watch News & Analysis 10/5/2003 Post a comment What's catching the attention of venture capitalists these days? Try wireless, FPGAs, and design-for-manufacturing, as TelASIC, Anadigm, and Sigma-C announced VC funding last week.
Jeda language simplifies hardware verification News & Analysis 10/3/2003 Post a comment Jeda is a new hardware verification language (HVL) that claims ease of use, flexibility, and power. In this first public tutorial, Jeda author Atsushi Kasuya and co-authors show how Jeda would be used to construct a hardware model and a testbench for a 4x4 crossbar switch.