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Content tagged with Design Tools (EDA)
posted in October 2004
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Mentor creates PCB design team collaboration technology
News & Analysis  
10/29/2004   Post a comment
Mentor Graphics Corp. has added a new server based PCB team collaboration technology to its Board Station and Expedition layout tools.
Application engine synthesis offers new design approach
News & Analysis  
10/29/2004   Post a comment
On-chip application engines can greatly speed algorithm execution, says Vinod Kathail (right), founder and CTO of Synfora. Kathail shows how "application engine synthesis" works, and suggests an evaluation process for choosing the right technology and tools.
CCS offers advanced delay calculation methodology
News & Analysis  
10/29/2004   Post a comment
Authors from Synopsys make the case for that company's new Composite Current Source (CCS) delay calculation technology, said to provide the accuracy needed for deep submicron designs.
Virginia Tech gets U.S. funding for verification training
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10/29/2004   Post a comment
The National Science Foundation will fund design verification courses at Virginia Tech's engineering department designed to overcome future roadblocks in complex designs.
Magma hits revised earnings, hints at Mentor Calibre competitor
News & Analysis  
10/28/2004   Post a comment
Magma Design Automation Inc. met guidance for its second quarter of fiscal 2005, posting revenue of $36.9 million, a 43 percent increase over the same quarter last year, in which Magma posted revenue of $25.8 million.
Sandwork waveform viewer works with Cadence AMS tools
News & Analysis  
10/28/2004   Post a comment
EDA startup Sandwork Design Inc. has collaborated with Cadence Design Systems Inc. to ensure its WaveView analog and mixed-signal waveform analysis tool can be used with Cadence's Virtuoso Aptivia Specification-Driven Environment and Cadence's Virtuoso UltraSim fast spice simulator.
System-Level-Design eröffnet neue FPGA-Perspektiven
Blog  
10/27/2004   Post a comment
Programmierbarkeit ist der Schlüssel zur heutigen Elektronik: Die Eigenschaften eines Produkts werden nicht mehr nur von der Schaltung, sondern zunehmend durch die Software definiert. Dies gilt in zunehmendem Maße auch für FPGA-Designs.Daraus ergeben sich weitreichende Konsequenzen für den Konstrukteur.
Synfora upgrades "algorithm-to-tapeout" synthesis tool
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10/26/2004   Post a comment
EDA startup Synfora Inc. has released a new version of its Pico Express "algorithm-to-tapeout" synthesis tool, with faster IP integration and verification and improved support for FPGA designs.
Mentor revoit à la baisse ses objectifs pour le 4ème trimestre
News & Analysis  
10/26/2004   Post a comment
Mentor Graphics Corp. ne se montre pas à la hauteur des espérances de Wall Street pour le troisième trimestre, en affichant un chiffre d’affaires de 162 millions de dollars, en hausse de 3 % par rapport aux 157 millions de dollars pour le même trimestre de 2003. Par ailleurs, la société réduit légèrement ses prévisions pour le quatrième trimestre, empruntant le même chemin que la plupart des fournisseurs de CAO.
Xpedion upgrades RF simulator, adds distributor in China
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10/25/2004   Post a comment
Xpedion Design Systems Inc. has released a speedier version of its GoldenGate RF simulator with the version 3.4 update. The company also announced it has signed Crescendo Technologies as its distributor in China.
Magma teams with Mentor and Logic Vision for test tools
News & Analysis  
10/25/2004   Post a comment
Magma Design Automation Inc. is ensuring its Blast RTL to GDSII tool lineup works with popular test tools, as the company announced interoperability partnerships with Mentor Graphics and separately with Logic Vision.
Software promises realtime test, product quality, performance insight
Product News  
10/25/2004   Post a comment
Enterprise software provider SigmaQuest is rolling out a new product that provides actionable information that can help ensure product intergrity and process integrity. Working with test-and-measurement partners National Instruments, ASSET-InterTech, and Agilent Technologies, the company is dishing up software that's been beta-tested with seven user organizations worldwide. It's billed as Web-architected product-quality and performance-intelligence software.
Cal Berkeley dean predicts server-farm-on-a-chip
News & Analysis  
10/23/2004   Post a comment
Software configurable processors arranged in a sea-of processor configuration on silicon will soon enable designers to put a server farm worth of compute power on a single IC, said U.C. Berkeley's Dean of the College of Engineering Richard Newton in his keynote at the Synopsys EDA Interoperability Developers forum here Thursday (Oct. 21).
Cadence annonce un bénéfice mais aussi un ralentissement des commandes
News & Analysis  
10/22/2004   Post a comment
Cadence Design Systems Inc. annonce un troisième trimestre bénéficiaire mais aussi un ralentissement des commandes.
EDA startup Luminescent emerges to address RET space
News & Analysis  
10/22/2004   Post a comment
A startup run by a former executive of Applied Materials Inc. has emerged and is developing products that could be a breakthrough in the resolution enhancement technology (RET) space.
Verisity exceeds Street in Q3
News & Analysis  
10/22/2004   Post a comment
Verification tool vendor Verisity Ltd. posted fiscal Q3 revenue of $15.5 million, a 29 percent increase from revenue of $12.0 million for the quarter ended September 30, 2003, and a 13 percent increase from revenue of $13.7 million for the quarter ended June 30, 2004.
Magma files countersuit against Synopsys
News & Analysis  
10/22/2004   Post a comment
Magma Design Automation Inc. filed a countersuit against Synopsys Inc.
Mentor misses Q3 earnings, lowers Q4 guidance
News & Analysis  
10/21/2004   Post a comment
Mentor Graphics Corp. narrowly missed Wall Street expectations for third quarter, reporting revenue of $162 million up 3 percent from $157 million for the same quarter in 2003. The company also lowered guidance slightly for Q4, following suit with most other EDA vendors.
New Synopsys timing model challenges Cadence's ECSM
News & Analysis  
10/21/2004   Post a comment
Seeking a more accurate approach to nanometer delay modeling, Synopsys revealed its composite current source (CCS) model at the Synopsys Interoperability Forum here Thursday (Oct. 21). But with Cadence Design Systems and Magma Design Automation backing Cadence's effective current source model (ECSM), EDA users will be confronted with two competing modeling formats.
A primer on processor-based emulation
News & Analysis  
10/21/2004   Post a comment
How does processor-based emulation work, and how does it compare to FPGA-based emulation? Cadence Design Systems' Ray Turner (right) walks you through the basics of processor-based emulation and shows how it handles clocking.
Cadence reports profit, but says bookings are slowing
News & Analysis  
10/20/2004   Post a comment
Cadence Design Systems Inc. reported net income of $20 million, or 7 cents per share on sales of $302 million in the third quarter, compared to a net loss of $14 million, or 5 cents per share on sales of $269 million in the year-ago quarter.
Catalytic adds key piece to ESL puzzle
Blog  
10/20/2004   Post a comment
There's a missing element to electronic system-level design; how do we get the C/C++ representation in the first place? By adding fixed-point capabilities to Matlab, startup Catalytic is providing an answer.
Mentor adds yield features to Calibre DRC/LVS tool
News & Analysis  
10/20/2004   Post a comment
Mentor Graphics Corp. has introduced a new add on to its Calibre DFM DRC/LVS tool that will help chip designers adhere to ever more stringent design rules and hopefully improve the yield of their designs.
ECSM sets new standard for timing model accuracy
News & Analysis  
10/19/2004   Post a comment
Cadence's Wei-Jin Dai (left) and Magma's Premal Buch team up to make the case for the effective current source model (ECSM), said to be more accurate than a scalable polynomial delay model proposed for the .lib library format.
Cadence claims industry's first 'yield diagnostics'
News & Analysis  
10/19/2004   Post a comment
Claiming to offer the industry's first "yield diagnostics" tools, Cadence Design Systems Tuesday (Oct. 19) introduced Encounter Diagnostics. The offering promises a new approach that speeds yield ramp-up time for nanometer IC designs.
Cadence, Magma go after Synopsys timing standard
News & Analysis  
10/19/2004   Post a comment
Physical design rivals Cadence Design Systems Inc. and Magma Design Automation are teaming up in what appears to be yet another attempt to loosen Synopsys Inc.'s stranglehold on IC timing.
Synopsys buys PCI Express IP vendor Cascade Semi
News & Analysis  
10/18/2004   Post a comment
Synopsys Inc. is continuing its shopping spree by acquiring PCI core vendor Cascade Semiconductor Solutions Inc. for an undisclosed amount.
Cadence to add assertion library to platform
News & Analysis  
10/18/2004   Post a comment
Cadence Design Systems Inc. said it will add new assertion-based verification (ABV) functionality and a new ABV library to its Incisive verification platform's Unified Simulator.
Chipdesign: Simulation ersetzt Trial-and-error
News & Analysis  
10/18/2004   Post a comment
Mit einer Simulationssoftware will der US-Startup Mirabilis Design Entwicklern von Chips und Automobilelektronik unter die Arme greifen: Simulieren statt wiederholen, heißt die Devise.
Measuring success before verification is completed
News & Analysis  
10/15/2004   Post a comment
Verisity's Coby Hanoch assures readers he's not crazy when he says a metric-driven methodology can help predict and ensure verification success.
Monterey users must find new options
News & Analysis  
10/15/2004   Post a comment
With Synopsys' decision to not continue or support Monterey Design Systems' products, and with support from Monterey only available through the end of the year, users must find other options " unless they want to take the risk of using unsupported software that won't see any further improvements or enhancements.
Digital RF techniques ease chip integration challenges
News & Analysis  
10/15/2004   Post a comment
You don't have to struggle to design and implement analog components on a chip, say Texas Instruments engineers including Bill Krenik (right). This article shows how you can employ digital RF techniques to process RF signals, using familiar tools and processes.
Forte upgrades timing diagram tool
News & Analysis  
10/15/2004   Post a comment
Claiming enhanced project management and timing interface design features, the Chronology division of Forte Design Systems has released version 7.0 of its TimingDesigner interactive timing analysis and diagramming product.
Objectif zéro bogue pour les tâches embarquées
Blog  
10/15/2004   Post a comment
Les systèmes embarqués d’aujourd’hui comportent couramment des milliers, voire des millions de lignes de code. Par ailleurs, le nombre d’ingénieurs logiciels qui œuvrent au sein d’une équipe de conception, tout comme leur budget de développement, est maintenant égal ou supérieur à celui de leurs homologues du secteur matériel. Les limites inhérentes aux solutions de vérification classiques font que près de la moitié des projets de développement des systèmes embarqués sont lancés avec plusieurs m
Aldec Brings Mixed VHDL/Verilog/SystemC Verification to Mainstream Designers
Product News  
10/14/2004   Post a comment
Riviera 2004.08 Supports SystemC at the Kernel-Level for Seamless Integration
LogicVision to acquire DFM yield specialist SiVerion
News & Analysis  
10/14/2004   Post a comment
Embedded software test specialist LogicVision Inc. on Thursday (Oct. 14) said it has entered into a definitive agreement to acquire SiVerion Inc. a provider of parametric yield analysis solutions.
Silicon Meets the Constraints of Tuner Design
News & Analysis  
10/13/2004   Post a comment
Televisions, VCRs, set-top boxes and broadband cable receivers all share a common element: the tuner. While all the other electronic elements in these devices have scaled down with shrinking semiconductor technologies, consumer applications typically use a bulky "tuner can" to implement this key function. Challenging constraints on tuner design are responsible for this technology holdout, but market forces are now bringing silicon tuners to the fore.
Integrated thermal designer analyzes complex ICs
Product News  
10/13/2004   Post a comment
Billed as the first stand alone thermal analysis tool that fully integrates with an industry-standard computer-aided design (ECAD) program, Package Thermal Designer (PTD) V2.0 from Harvard Thermal works with the Encore package-design system from Synopsys to automatically create highly-detailed thermal models at the component level (BGA, multi-chip and stacked die packages). PTD, launched directly from within Encore, constructs a three-dimensional thermal model using detailed design data includin
Synopsys rachète ISE, développeur de DFM, pour 95 millions de dollars
News & Analysis  
10/13/2004   Post a comment
Continuant sur la voie des acquisitions, Synopsys Inc. a annoncé lundi (11 octobre) le rachat d’Integrated Systems Engineering AG (ISE), développeur d’un logiciel de DFM (Design for Manufacturing, à savoir la conception d’un produit en fonction de sa compatibilité avec les opérations de fabrication), pour un montant de 95 millions de dollars.
Confirmation du rachat de Monterey Design par Synopsys
News & Analysis  
10/12/2004   Post a comment
Des sources proches de la direction confirment à EE Times le rachat, par Synopsys Inc., du fabricant d’outils en difficulté Monterey Design Systems.
Update: Synopsys gains TCAD, DFM with ISE acquisition
News & Analysis  
10/11/2004   Post a comment
Synopsys Inc. is rounding out its TCAD and DFM tool lines with the $95 million acquisition of ISE, the Swiss TCAD provider.
Update: Synopsys gains TCAD, DFM with ISE acquisition
News & Analysis  
10/11/2004   Post a comment
Synopsys Inc. is rounding out its TCAD and DFM tool lines with the $95 million acquisition of ISE, the Swiss TCAD provider.
Update: Synopsys says it will shelve Monterey's tools
News & Analysis  
10/11/2004   Post a comment
Synopsys Inc. said it will acquire most of Monterey's assets except customer contracts and will shelve all existing Monterey tools.
Selon le président de Magma, l’activité de conception ne connaît aucun ralentissement
News & Analysis  
10/11/2004   Post a comment
Au début de la semaine dernière, Magma Design Automation a réduit de 50 % ses prévisions trimestrielles de commandes. Lors d’une conférence téléphonique avec les analystes, les dirigeants de Magma ont néanmoins réfuté tout ralentissement des activités de conception pour les nœuds de procédés 90 et 65 nm. « Il n’y a absolument pas de ralentissement dans la conception 90 nm et 65 nm ni dans la conception en général », a alors affirmé le président de Magma, Roy Jewell. « Nos clients sont toujours
Synopsys acquires DFM developer ISE for $95 million
News & Analysis  
10/11/2004   Post a comment
Continuing on its acquisition spree, Synopsys Inc. Monday (Oct. 11) said that it has acquired Integrated Systems Engineering AG (ISE), a developer of design-for-manufacturing (DFM) software, for $95 million.
System on chip wrestles RF and digital integration issues
News & Analysis  
10/11/2004   Post a comment
The schedule is slipping, back-end redesign looms large, the IP is cobbled together with baling twine, tool sets are ticking everybody off and a cave-in just extinguished the light at the end of the tunnel. Is prayer the last refuge of an SoC design team?
Designing an optimal wireless SoC
News & Analysis  
10/11/2004   Post a comment
The semiconductor industry is expected to provide complete and optimal system solutions, including silicon, firmware, external components, board layout (in the form of Gerber files) and even, in some cases, man-machine interface software. These highly integrated systems-on-chip, particularly wireless SoC devices, require developers to pay considerable attention to optimizing trade-offs among cost, power consumption, size, performance and scalability. But achieving the right balance and associate
IP reuse simplifies SoC design, verification
News & Analysis  
10/11/2004   Post a comment
Larger, more-complex digital designs demand inventive techniques and tools that simplify the design and verification process. This is a response to both design complexity challenges and the new opportunities of increased silicon real estate. For example, at this year's Design Automation Conference, Gary Smith of Dataquest observed that the advent of 65-nanometer processes marked the first time that system developers were unable to use all of the available design gates. This gap between fabricati
Restoring predictability in SoC integration
News & Analysis  
10/11/2004   Post a comment
Of the more than 1,000 IC projects reviewed in a March study by Numetrics Inc. (Cupertino, Calif.), 85 percent missed their target delivery date. Just as alarming, the average project overran its schedule by a factor of 53 percent. Numbers like these expose an ugly truth: System-on-chip integration is nowhere close to being predictable for most teams. The drive to build ever-bigger chips with their attendant submicron effects has left physical designers battling too much complexity and juggling
RF integration: Changing the face of test
News & Analysis  
10/11/2004   Post a comment
In the wireless world, the only constant is change. With the push for single-chip implementations of wireless products, new radio architectures are emerging. This can be seen in mobile phones, wireless-LAN and Bluetooth applications, and more. In the face of integration, fundamental changes must occur in test to ensure quality product while minimizing test costs.
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