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posted in October 2005
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Lattice rolls out ispLEVER 5.1 programmable logic design tools
News & Analysis  
10/31/2005   Post a comment
Lattice Semiconductor announced the immediate availability of the ispLEVER 5.1 programmable logic design tool suite.
I-Logix unveils Statemate 4.1 for auto, aerospace modeling
Product News  
10/31/2005   Post a comment
I-Logix has released a new version of its Statemate 4.1 unified modeling language suite with additional workflow capabilities that allow teams of developers in applications such as automotive and aerospace to coordinate system specification.
Cadence now trading solely on Nasdaq
News & Analysis  
10/31/2005   Post a comment
Cadence Design Systems, EDA's largest company, is now being traded exclusively on the Nasdaq National Market.
Verifying large models in RTL simulation
News & Analysis  
10/31/2005   Post a comment
Using Silicon Graphics' ccNUMA memory architecture as an example, ASIC designer Debra Klopfenstein shows how you can efficiently represent extremely large models in RTL simulation environments.
New EDA startup promises 'package-aware' chip design software
News & Analysis  
10/28/2005   Post a comment
Rio Design Automation is expected to launch Monday with a goal of bridging the gap between the design of ICs and packages and a chip's integration with the rest of the electronics system.
EDA startup forms technical advisory board
News & Analysis  
10/28/2005   Post a comment
EDA startup Pyxis Technology named Warren Grobman, Mark McDermott, David Pan and Riko Radojcic to the company's newly created technical advisory board.
Magma reports increased loss on record quarterly revenue
News & Analysis  
10/27/2005   Post a comment
Magma Design Automation reported company-record quarterly revenue of $39.9 million for its fiscal second quarter, up 8 percent from the same period of its fiscal 2005.
Virage Logic revenue on par with fiscal 2004
News & Analysis  
10/27/2005   Post a comment
Virage Logic reported fiscal fourth quarter 2005 revenue of $12.8 million, down 16 percent from the $15.3 million that the company reported for the fourth quarter of fiscal 2004 and up 7 percent from the $12 million that the company reported for the third quarter of fiscal 2005.
International EDA veteran joins Sigma-C
News & Analysis  
10/27/2005   Post a comment
Microlithography simulation provider Sigma-C Software named EDA veteran Dennis Nye vice president of sales.
Cadence posts Q3 revenue increase
News & Analysis  
10/26/2005   Post a comment
Cadence Design Systems' third-quarter earnings report reflects "smooth and steady growth" resulting from new EDA business, according to Mike Fister, Cadence president and CEO.
Lattice, partners offer programmable PCI Express solution
Product News  
10/26/2005   Post a comment
Lattice Semiconductor introduced a low-cost programmable PCI Express solution that incorporates the LatticeECP and LatticeEC field-programmable gate array (FPGA) devices, the Genesys Logic GL9711 PCI Express PHY and Northwest Logic's PCI Express IP core.
Magma sues Synopsys for patent infringement
News & Analysis  
10/26/2005   Post a comment
The protracted legal tussle between electronic design automation rivals Magma Design Automation Inc. and Synopsys Inc. took another turn. This time, Magma sued Synopsys on the grounds that claiming that Synopsys' Astro and IC Compiler products infringe a Magma patent.
Magma files patent infringement claim against Synopsys
News & Analysis  
10/26/2005   Post a comment
Claiming to have patented technology behind a common data model that unites EDA tools, Magma Design Automation has charged that Synopsys' Astro and IC Compiler products infringe a Magma patent.
Altera's stock slides after analyst downgrades
News & Analysis  
10/26/2005   Post a comment
Shares of Altera dropped 7 percent to close at $16.41 after several analysts downgraded the company's stock.
Telelogic brings SysML to its TAU G2 system modeling suite
News & Analysis  
10/25/2005   Post a comment
In anticipation of SysML's approval as a standard, Telelogic, Inc. has added support for the proposed Systems Modeling Language spec to its TAU G2 system modeling tool suite.
Jazz, Xpedion partner on RFIC design environment
News & Analysis  
10/25/2005   Post a comment
Xpedion Design Systems and Jazz Semiconductor announced a partnership to deliver a qualified model and simulation environment for next generation radio frequency IC design.
Survey finds verification tool use largely unchanged from 2004
News & Analysis  
10/25/2005   Post a comment
A verification census conducted by an EDA tool user Web site yielded results that were "jaw-droppingly" similar to last year's, according to John Cooley, the survey's moderator.
Altera releases enhanced Quartus II PLD design tool
News & Analysis  
10/25/2005   Post a comment
Altera introduced an enhanced version of its Quartus II design software that supports the company's new Stratix II GX field-programmable gate array family.
Virtio adds cycle-approximate simulation to virtual platforms
Product News  
10/24/2005   Post a comment
Virtio has extended its Virtual Platform technology to support highly accurate timing analysis in software simulation.
Researchers propose approach to cut design validation time
News & Analysis  
10/24/2005   Post a comment
Five Indian researchers from the have proposed a new approach to formal property verification.
Managing variations in IC physical design
Design How-To  
10/24/2005   Post a comment
The CTO of Sierra Design Automation reviews the causes and consequences of variability in physical IC design, and shows how it can be modeled and managed.
Freescale exec says central design pays dividends
News & Analysis  
10/21/2005   Post a comment
Changes in Freescale Semiconductor's approach to chip design, including centralization of methodologies and tools and the appointment of a renowned design manager, are contributing to improvements in the company's bottom line, according to Sumit Sadana, senior vice president of strategy and business development.
SEMI honors Cognex, EDA pioneer Koford
News & Analysis  
10/21/2005   Post a comment
Semiconductor Equipment and Materials International said the 2005 SEMI Award for North America would be presented to the team of Bob Shillman, Bill Silver and Marilyn Matz for contributions to machine vision inspection for the semiconductor industry.
PDF Solutions reports record Q3 revs, income up
News & Analysis  
10/20/2005   Post a comment
PDF Solutions reported record third quarter revenue and a dramtic increase in net income, based on generally accepted accounting principles (GAAP).
Mentor posts strong 3Q bookings, record revenue
News & Analysis  
10/20/2005   Post a comment
After posting dismal results during the first two quarter of 2005, Mentor Graphics posted a slight third quarter profit on revenue of $164.8 million. The company's bookings were up 15 percent for the quarter.
Third quarter revenue, net income up at Synplicity
News & Analysis  
10/20/2005   Post a comment
Synplicity reported third quarter revenue of $15.9 million, up 13 percent from the same period of 2004 and up 5 percent from the previous quarter.
Virage Logic, MIPS Technologies partner on IP kits
News & Analysis  
10/20/2005   Post a comment
MIPS Technologies and Virage Logic have forged an alliance to deliver the first in a series of new core-optimized intellectual property (IP) kits.
Magma accuses Synopsys of antitrust violations
News & Analysis  
10/20/2005   Post a comment
Magma Design Automation believes a patent infringement suit filed by rival Synopsys violates U.S. antitrust law, Magma said in a court filing.
Mohsen defense motions court to dismiss charges
News & Analysis  
10/20/2005   Post a comment
Lawyers for former Aptix CEO Amr Mohsen have filed motions asking a U.S. District Court to dismiss many of the charges facing their client, including solicitation to commit murder.
Integrating analog IP: The chip-level verification challenge
News & Analysis  
10/19/2005   Post a comment
It's an oft' told tale that an IC company, even though it focuses on its core competancy, still needs to deliver a complete system-on-chip including the analog. What happens if unforseen problems occur, such as can happen in the confusion of the analog world's tower of Babel with its variety of languages for block design. Here is some clear-headed thinking that cuts right through the confusion, by one who has been there.
Virage adds Jim Bailey as VP of sales
News & Analysis  
10/18/2005   Post a comment
Virage Logic appointed industry veteran Jim Bailey vice president of worldwide sales.
SynTest secures U.S. patent for DFT technology
News & Analysis  
10/18/2005   Post a comment
SynTest Technologies was granted 33 claims last week on a U.S. patent for its invention of at-speed testing of asynchronous multi-clock, multi-frequency designs using automatic test pattern generation or logic built-in self test schemes.
Analyzer said to validate DFT before prototypes
News & Analysis  
10/17/2005   Post a comment
Asset InterTech introduced a design-for-test (DFT) analyzer that the company claims reduces manufacturing and test costs by validating the boundary-scan DFT features in a circuit board design before any prototypes are assembled.
Synfora announces interface to Mentor's ModelSim
News & Analysis  
10/17/2005   Post a comment
Synfora announced the availability of an integrated product interface for Synfora PICO Express and the ModelSim simulation environment from Mentor Graphics.
Cadence pushes for accelerating IEEE P1647 e standardization
News & Analysis  
10/17/2005   Post a comment
Cadence Design Systems said it has stepped up its support for the IEEE P1647 e standardization effort in response to user demand.
Registration open for international SoC conference
News & Analysis  
10/17/2005   Post a comment
The third international System-on-Chip (SoC) conference and exhibition will be held on the 1st and 2nd of November 2005 in Newport Beach, California.
Design-for-test analyzer validates boundary-scan
Product News  
10/17/2005   Post a comment
ASSET InterTech is readying a 3-in-1 IEEE-1149.1/JTAG boundary-scan test tool that promises to reduce manufacturing and test costs. Here's a preview.
Tool suite 'lays foundation' for extending TCAD to DFM
News & Analysis  
10/17/2005   Post a comment
Synopsys introduced a new TCAD tool suite that integrates features of former Technology Modeling Associates and Integrated Systems Engineering products as well as adding new capabilities that enable TCAD to be used in the manufacturing space.
Test takes new role in yield improvement
News & Analysis  
10/17/2005   Post a comment
By identifying failure mechanisms, new test methodologies can support design for manufacturability (DFM) efforts aimed at improving yields, says Mentor Graphics' Mark Chadwick.
Flex technology key to next-gen system design, report says
News & Analysis  
10/14/2005   Post a comment
Flexible and flex-rigid substrates are now a key emerging technology in next-generation electronic system design and development and IC packaging, according to a new report by Research and Markets.
OpenAccess Conference set for Nov. 10
News & Analysis  
10/12/2005   Post a comment
The Silicon Integration Initiative (Si2) said OpenAccess Conference will be held Nov. 10 at Semiconductor Equipment and Materials International's headquarters.
Denali CTO says software, verification first
News & Analysis  
10/12/2005   Post a comment
Software content and verification strategy must be considered at the earliest stages of a design, according Mark Gogolewski, chief technology officer at Denali Software Inc.
Marvell introduces next-gen Discovery system controller
News & Analysis  
10/12/2005   Post a comment
Marvell Tuesday released what it said was the industry's most powerful system controller for Power Architecture-based microprocessors, the Discovery V.
Shrenik Mehta elected chair of Accellera
News & Analysis  
10/11/2005   Post a comment
Sun Microsystems' Shrenik Mehta has been elected chair of Accellera following three terms as the organization's vice chair.
Denali offering verification IP for CE-ATA
News & Analysis  
10/11/2005   Post a comment
Denali Software is making its PureSpec verification intellectual property available for the verification of CE-ATA designs.
Zuken releases new Cadstar pcb solution
News & Analysis  
10/11/2005   Post a comment
Zuken announced the availability of the latest version of the company's Cadstar Windows-based printed circuit board design solution.
Static and dynamic modeling for high-density memories
News & Analysis  
10/10/2005   Post a comment
Modeling high-density memories with HDLs can be a bottleneck. Sharan Basappa of HCL Technologies' VLSI group shows new ways of modeling with static and dynamic memories.
KLA-Tencor offers 'litho-aware' inspection
News & Analysis  
10/7/2005   Post a comment
KLA-Tencor has formally introduced a full-chip process window inspection system for post-RET (resolution enhancement technology) reticle design layout inspection.
Design, manufacturing worlds collide at Bacus
News & Analysis  
10/7/2005   Post a comment
If there was a shred of doubt remaining about the magnitude at which IC design and manufacturing convergence is taking place, it was laid to rest this week at the 25th annual Bacus Photomask Technology symposium.
Mentor adds concurrent HDL checking to tool suite
News & Analysis  
10/7/2005   Post a comment
Mentor Graphics Corp. said the latest version of the HDL Designer Series tool suite includes a concurrent design checking and creation environment.
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