Verifying large models in RTL simulation News & Analysis 10/31/2005 Post a comment Using Silicon Graphics' ccNUMA memory architecture as an example, ASIC designer Debra Klopfenstein shows how you can efficiently represent extremely large models in RTL simulation environments.
Virage Logic revenue on par with fiscal 2004 News & Analysis 10/27/2005 Post a comment Virage Logic reported fiscal fourth quarter 2005 revenue of $12.8 million, down 16 percent from the $15.3 million that the company reported for the fourth quarter of fiscal 2004 and up 7 percent from the $12 million that the company reported for the third quarter of fiscal 2005.
Cadence posts Q3 revenue increase News & Analysis 10/26/2005 Post a comment Cadence Design Systems' third-quarter earnings report reflects "smooth and steady growth" resulting from new EDA business, according to Mike Fister, Cadence president and CEO.
Magma sues Synopsys for patent infringement News & Analysis 10/26/2005 Post a comment The protracted legal tussle between electronic design automation rivals Magma Design Automation Inc. and Synopsys Inc. took another turn. This time, Magma sued Synopsys on the grounds that claiming that Synopsys' Astro and IC Compiler products infringe a Magma patent.
Freescale exec says central design pays dividends News & Analysis 10/21/2005 Post a comment Changes in Freescale Semiconductor's approach to chip design, including centralization of methodologies and tools and the appointment of a renowned design manager, are contributing to improvements in the company's bottom line, according to Sumit Sadana, senior vice president of strategy and business development.
SEMI honors Cognex, EDA pioneer Koford News & Analysis 10/21/2005 Post a comment Semiconductor Equipment and Materials International said the 2005 SEMI Award for North America would be presented to the team of Bob Shillman, Bill Silver and Marilyn Matz for contributions to machine vision inspection for the semiconductor industry.
Integrating analog IP: The chip-level verification challenge News & Analysis 10/19/2005 Post a comment It's an oft' told tale that an IC company, even though it focuses on its core competancy, still needs to deliver a complete system-on-chip including the analog. What happens if unforseen problems occur, such as can happen in the confusion of the analog world's tower of Babel with its variety of languages for block design. Here is some clear-headed thinking that cuts right through the confusion, by one who has been there.
SynTest secures U.S. patent for DFT technology News & Analysis 10/18/2005 Post a comment SynTest Technologies was granted 33 claims last week on a U.S. patent for its invention of at-speed testing of asynchronous multi-clock, multi-frequency designs using automatic test pattern generation or logic built-in self test schemes.
Analyzer said to validate DFT before prototypes News & Analysis 10/17/2005 Post a comment Asset InterTech introduced a design-for-test (DFT) analyzer that the company claims reduces manufacturing and test costs by validating the boundary-scan DFT features in a circuit board design before any prototypes are assembled.
Design, manufacturing worlds collide at Bacus News & Analysis 10/7/2005 Post a comment If there was a shred of doubt remaining about the magnitude at which IC design and manufacturing convergence is taking place, it was laid to rest this week at the 25th annual Bacus Photomask Technology symposium.
Battle-hardened veterans of the electronics industry have heard of the “connected car” so often that they assume it’s a done deal. But do we really know what it takes to get a car connected and what its future entails? Join EE Times editor Junko Yoshida as she moderates a panel of movers and shakers in the connected car business. Executives from Cisco, Siemens and NXP will share ideas, plans and hopes for connected cars and their future. After the first 30 minutes of the radio show, our listeners will have the opportunity to ask questions via live online chat.