Test methods identify small delay defects Design How-To 10/30/2006 Post a comment Today's systematic and more subtle random defects are not only decreasing yields, but are also increasing the number of test escapes, or defective parts per million (DPPM) shipped out. One of the biggest challenges for design for test (DFT) and test engineers is how to improve test quality without dramatically increasing the cost of test.
Electronic design processes (EDP) 2007 issues call for papers News & Analysis 10/27/2006 Post a comment The 2007 EDP Workshop will be held on April 12 and 13 at the Monterey Beach Hotel, in Monterey California. The themes for the workshop are: power methodologies and design for manufacturing. The program committee is soliciting papers and proposals for special/panel sessions.
Nvidia calls for increasing test quality News & Analysis 10/26/2006 Post a comment Nvidia's Chris Malachowsky detailed some troubling trends in his keynote at the International Test Conference, saying, "The costs for ASIC development are growing to over $46 million with test costs about $2 million of the total."
Ciranova wins $4M, boosts staff News & Analysis 10/25/2006 Post a comment Gearing up for its marketplace entry, analog EDA startup Ciranova has closed a $4 million round of venture funding, and named a new COO and vice president of business development.
VSPs spur on-time delivery of embedded automotive systems software: Part 2 Design How-To 10/24/2006 Post a comment Virtual systems prototypes offer high-performance simulation models that allow engineers to fine tune systems designs using realistic software loads without the need for expensive hardware design. Part 2 covers designing in quality, rather than testing for quality, with applicability to single unit and distributed controller platforms.
Need evolving for next-generation EDA tools, report says News & Analysis 10/24/2006 Post a comment The entire electronics industry depends on efficiency and innovation of EDA tools, which is becoming even more important with the continuing rise in reduction in ICs from micro-to nanoscale dimensions, according to a new report by research analyst Frost & Sullivan.
Jungo releases WinDriver USB/PCI Version 8.11 Product News 10/23/2006 Post a comment Jungo Software's WinDriver version 8.11 now supports PowerPC 64 bit architectures on Linux 2.6.x Kernels, including the latest 2.6.17-18. The new version of WinDriver also includes support for Fedora Core 6 pre-releases.
European initiative promotes new standards-based SoC design environments News & Analysis 10/18/2006 Post a comment A group of 15 leading European Semiconductor companies, Intellectual Property (IP) vendors, Electronic Design Automation (EDA) companies and academic institutions specializing in advanced silicon chip design today announced that they are working jointly on the SPRINT Project to keep Europe at the forefront of System-on-Chip (SoC) development.
RF software simulates everything from waveguides to metamaterials Product News 10/17/2006 Post a comment Here's a simulation package for the design of RF, microwave, and photonics components. The software lets you observe components and systems that deal with propagating electromagnetic waves, letting you study the interconnection of electromagnetics phenomena with heat transfer, structural mechanics---and more.
Strengthening the backbone Automotive DesignLine Blog 10/17/2006 Post a comment If Airbus had integrated wiring design tools, they wouldn't find themselves in an extended delivery delay crisis for the first A380 super jumbo jets.
Metrics measure IC design productivity Design How-To 10/16/2006 Post a comment IC design productivity is often thought of as an elusive term. As the old axiom states, "you cannot improve what you cannot measure." A practical methodology for improving productivity requires first identifying actionable and relevant metrics to measure that do not burden the design process or the design team with excessive overhead.
Betting on Russia's promise News & Analysis 10/16/2006 Post a comment
The design automation tool leaders are sowing seeds in Russia to grow the next generation of chip designers. Cadence, Mentor Graphics and now Synopsys have all forged ties with the Moscow Institute of Electronics Technology, one of Russia's elite high-tech learning centers, by donating tools and instructing graduate students. "Teaching students how to work most effectively with industry-leading electronic design tools ensures a work force well-prepared to advance Russia's growing electronics i
Synopsys subpoenas Mentor over PTO request News & Analysis 10/13/2006 Post a comment Synopsys has served fellow EDA vendor Mentor Graphics a subpoena demanding certain documents related to Mentor's request for reexamination of two Magma Design Automation Inc. patents by the U.S. Patent and Trademark Office.
DSP libraries are optimized for Power744x processor Product News 10/13/2006 Post a comment VMETRO has launched VSIPlus, a bundle of C-libraries for DSP processing that is optimized for the Power744x processor. The libraries support VxWorks 5.5 and products such as the Phoenix VPF1 DSP VXS board. The bundle includes VSIPL, CSIPL and VecLib open-standards.
Does ESL need another language? Blog 10/13/2006 Post a comment Systems architects need to describe the requirements and architecture of a system without the limits imposed by a presumed implementation choice. Some of the projects aiming to develop a true architectural language for the ESL market show both technical and financial promises.
Blog Make a Frequency Plan Tom Burke 17 comments When designing a printed circuit board, you should develop a frequency plan, something that can be easily overlooked. A frequency plan should be one of your first steps ...