NASA expands Altium tool use News & Analysis 10/30/2007 Post a comment NASA's Johnson Space Center has selected Altium Designer as the standard to unify electronic design for NASA's leading spaceflight-related research center.
Expanding the DFM market Blog 10/30/2007 Post a comment Apache's acquisition of Optimal is another clear signal that the EDA industry is adapting to provide designers with tools that allow them to work on the entire system, not just parts that have different physical characteristics.
Accelerating Functional Verification Design How-To 10/29/2007 Post a comment Rising design complexity coupled with increasingly intricate hardware/software interactions and customers' rising demand for lower power operation are placing new demands on SoC functional verification strategies. Together these trends are threatening SoC predictability and product development schedules.
FPGA debugger works at full speed Product News 10/24/2007 Post a comment EDA startup EDAptability has announced the availability of its FPGA and ASIC debugging tool TotalScope. With a combination of RTL level elaboration, model extraction and modification techniques with simulation, the tool offers unrivaled signal visibility, the company claims.
Magma Unveils Talus ATPG and Talus ATPG-X Product News 10/15/2007 Post a comment Magma Unveils Talus ATPG and Talus ATPG-X " Expands Design-for-Test Capabilities with Physically Aware ATPG and On-Chip Compression. Advanced ATPG products support simultaneous analysis of multiple fault models, leverage multi-threading and on-chip compression to improve quality and reduce turnaround time and costs of nanometer ICs.
In-System Silicon Validation and Debug Design How-To 10/15/2007 Post a comment This is the third and final article in a series about silicon validation. Part 1 described the silicon validation problem and the basic requirements of an effective and scalable solution. Part 2 introduced the new approach and its basic applications. Part 3 presents the experience provided by four commercial devices implemented with the ClearBlue solution.
EDAC hosts seminar on export controls News & Analysis 10/15/2007 Post a comment Kritzer, the Director of the U.S. government's Office of National Security and Technology Transfer Controls, will address a broad range of issues related to technology transfer at an Oct. 18 seminar in San Jose.
Green Hills Software supports Fujitsu's FR MCU series Product News 10/14/2007 Post a comment Green Hills Software has announced that its product suite, including the MULTI version 5.0 IDE, TimeMachine tool suite, Green Hills compilers, and SuperTrace Probe, are now available for the Fujitsu FR60, FR70, and FR80 32-bit RISC microcontrollers.
Micro Magic Announces MAX-3D Product News 10/9/2007 1 comment Wafer stacking is becoming more ubiquitous for two principal reasons: shrinking space on the PC Board, and process requirements for mixed technology designs. A new product from Micro Magic aims at aiding the integration of various dies into one IC package.
AWR and NXP Release LDMOS Simulation Library Product News 10/9/2007 Post a comment Applied Wave Research, Inc. (AWR) has released a Microwave Office® 2007 design software simulation library that features NXP Semiconductor's sixth-generation laterally-diffused metal oxide semiconductor (LDMOS) devices.
Signoff for Manufacturability Design How-To 10/8/2007 Post a comment Designing at the 45nm node combines huge risks with the potential for huge rewards. In order to take full advantage of 45nm process capabilities, it is important to understand and quantify process and manufacturing variations to improve accuracy, reduce pessimism, and support informed decisions about yield and performance tradeoffs.
New error comparison scheme proposed for design rule checking flows News & Analysis 10/2/2007 Post a comment A new flow to vastly simplify the task of comparing design rule checking errors between two tools, tool versions, or runsets while simultaneously helping design automation teams hike productivity several times (already tested by design teams in Intel) has been proposed at a recently held VLSI design and test meet.
In-System Silicon Validation and Debug: Part 2 Design How-To 10/2/2007 Post a comment This is the second in a series of three articles on silicon validation, introducing a new approach and some basic applications. Part 1 presented the silicon validation problem and the requirements of an effective and scalable solution. Part 3 will analyze the silicon results of four devices designed with the approach described here.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments