Peter Alfke Remembered, 1931-2011 Engineering Pop Culture! 10/31/2011 5 comments My friend Mike Santarini, publisher of Xcell Journal at Xilinx just told me of the passing of Peter Alfke, who was with Xilinx for more than 20 years.
Samsung, Cadence tout collaboration on SoC News & Analysis 10/25/2011 Post a comment Executives from Samsung's foundry unit and EDA vendor Cadence Design Systems say their collaboration on Ambarella's new HD digital camera SoC recalls another era before the fabless-foundry model evolved.
HSpice creator Ashawna Hailey dies News & Analysis 10/24/2011 2 comments Ashawna Hailey, co-founder of EDA software firm Meta-Software and a creator of circuit simulation program HSpice, died earlier this month at the age of 62.
Cadence CEO: Chip execs eye China, India News & Analysis 10/21/2011 6 comments Lip-Bu Tan, chief executive at Cadence Design Systems, says semiconductor industry leaders spend a lot of time thinking about China and India, because those markets will see explosive growth in chip consumption.
EDA/IP Weekly Roundup Blog 10/19/2011 Post a comment There are often many news items that are not worth writing a full blog about, but may still be of interest to people. This is a roundup of those items…
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments