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posted in October 2011
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New surveillance camera reference design from Lattice and Valens Semiconductor
Product News  
10/31/2011   1 comment
Comprehensive HDBaseT reference design for the surveillance market uses LatticeECP3 FPGA and Valens’ VS100 HDBaseT chipset
Peter Alfke Remembered, 1931-2011
Engineering Pop Culture!  
10/31/2011   5 comments
My friend Mike Santarini, publisher of Xcell Journal at Xilinx just told me of the passing of Peter Alfke, who was with Xilinx for more than 20 years.
SiliconBlue is sampling three new ultra-low-power 40nm FPGAs
Product News  
10/31/2011   Post a comment
New “Los Angeles” ultra-low-power 640, 1K and 4K LP and HX devices sampling; world’s smallest footprint, plastic 0.4mm 2.5x2.5mm BGA available now!
Tool tackles hardware software codesign for ARM-based FPGAs
Blog  
10/31/2011   2 comments
Hardware/software co-design available for ARM-based FPGA designers using Space Codesign…
My mother’s twisted relationship with Lord Voldemort
Programmable Logic DesignLine Blog  
10/31/2011   24 comments
I have to admit that my eyebrows went up higher than usual when my mother informed me that she used to bounce Lord Voldemort on her knee when he was a little lad…
Travel Nightmares: Propellors?
Blog  
10/31/2011   Post a comment
David Ashton fights for seats - any seats as he hops around the world on staff tickets...
What were they thinking: Pizza cutters galore
Blog  
10/28/2011   Post a comment
For some fun this week, I turn to pizza – one of my favorite weekend foods and look at ways to cut the pizza…
ARM Cortex-A9 MPCore Fast Processor Models Provided by Imperas and OVP
Product News  
10/27/2011   Post a comment
Imperas has released its models of the Cortex-A9 MPCore and Cortex-A5 UP ARM processor cores, including the 1, 2, 3, and 4-core versions of the Cortex-A9 MPCore.
Freescale, Green Hills team on virtualization
News & Analysis  
10/27/2011   Post a comment
Freescale Semiconductor and Green Hills Software announced a new alliance to expand the roll of system virtualization technology in ARM-based embedded and mobile applications.
EDA/IP Weekly Roundup
Blog  
10/26/2011   Post a comment
OCP, Mentor, Synopsys, Open Silicon, NextOp, Numetrics and the Portland group made the lineup today. See here for their news…
First sighting of Cadence’s virtual prototype
Blog  
10/26/2011   Post a comment
Cadence and Xilinx are teaming up to provide system-level verification via a virtual platform for the Zynq family of devices…
Simple ways to manage different clock frequencies of audio codecs
Design How-To  
10/26/2011   Post a comment
By proper reconfiguration of the digital filters, sample rate conversion and flexible clock frequency choices, a wide range of audio-video applications can be supported with modern audio codecs.
How it was: Life in the typing pool (I)
Programmable Logic DesignLine Blog  
10/26/2011   8 comments
In which my mother relates how, in September 1948, she was eager to start work on her first day as a qualified Shorthand Typist...
Xilinx and Cadence introduce an Extensible Virtual Platform
Product News  
10/26/2011   1 comment
Virtual platform allows software developers to start developing Code for the Zynq-7000 Extensible Processing Platform
Xilinx Zynq-7000 news from ARM TechCon
News & Analysis  
10/26/2011   Post a comment
Xilinx launches open source Linux Support and developer community for its ARM processor-based programmable SoC – the Zynq-7000 Extensible Processing Platform
Wow – Silego Technology sees 1127% growth!
Programmable Logic DesignLine Blog  
10/26/2011   Post a comment
Deloitte’s 2011 Technology Fast 500 recognizes Silego Technology as one of the fastest growing technology companies in North America
TSMC-backed design house adopts ASIC model
News & Analysis  
10/26/2011   Post a comment
Global Unichip, a 13-year-old design services vendor with close ties to TSMC, has revamped its business model to focus on becoming a flexible, full-service fabless ASIC vendor.
Yield optimization through MLR techniques
Design How-To  
10/25/2011   Post a comment
This paper describes a method to improve yield by using more accurate models associated with wafer level process variations…
Samsung, Cadence tout collaboration on SoC
News & Analysis  
10/25/2011   Post a comment
Executives from Samsung's foundry unit and EDA vendor Cadence Design Systems say their collaboration on Ambarella's new HD digital camera SoC recalls another era before the fabless-foundry model evolved.
Rambus engineers author book on signal integrity
Blog  
10/25/2011   Post a comment
New book by Rambus engineers covers high speed signaling, jitter modeling, analsysis, budgeting and more…
New Xilinx Virtex-7 2000T FPGA provides equivalent of 20 million ASIC gates
Product News  
10/25/2011   4 comments
Xilinx ships world’s highest capacity FPGA and shatters industry record for number of transistors
Xilinx announces world’s highest capacity FPGA
News & Analysis  
10/25/2011   1 comment
Virtex-7 2000T FPGA from Xilinx uses 2.5D IC stacked silicon interconnect technology to deliver 6.8 billion transistors
How it was: The inability to transition from one technology to another
Blog  
10/25/2011   2 comments
Over the years I’ve met guys who grew up working with one technology who couldn’t make the transition to a new technology...
Piiigs iiiin Spaaace
Programmable Logic DesignLine Blog  
10/25/2011   10 comments
It’s not that I’d forgotten the Muppet Show per se – more that I rarely think about it...
Digital filter design wizard for FIR and IIR filter implementations
Product News  
10/25/2011   Post a comment
This high-level software tool uses a design approach that walks the user through a series of easy to navigate dialog screens that contain instructional messages for each of the steps.
Benchtop EMI scans speed time-to-market
Design How-To  
10/25/2011   Post a comment
Designers of safety-critical systems are using benchtop very-near-field EMI scanning to facilitate rapid resolution of electromagnetic design issues.
One on one with lead designer of Cortex-A7
Semi Conscious  
10/24/2011   Post a comment
Highlights from a brief sit down with Peter Greenhalgh, an ARM engineer who served as the lead designer on the Cortex-A7 core.
Atrenta and Cadence team up on high-level synthesis flow
Blog  
10/24/2011   1 comment
Atrenta and Cadence team to provide a back-end rule set aimed at increasing the confidence in the quality of results produced from high-level synthesis.
HSpice creator Ashawna Hailey dies
News & Analysis  
10/24/2011   2 comments
Ashawna Hailey, co-founder of EDA software firm Meta-Software and a creator of circuit simulation program HSpice, died earlier this month at the age of 62.
Antique micromosaics are simply incredible
The Engineering Life - Around the Web  
10/24/2011   7 comments
I’d never heard about this art form before, so I just took a quick stroll around the Internet to discover that...
Travel Nightmares: delays and the consequences
Blog  
10/24/2011   1 comment
For this travel nightmares edition we have two stories about the impact that delays can have. In one case the bags and the people went by different routes and the other resulted in an extended trip…
Xilinx boasts 200+ design wins for 7 Series FPGAs
Programmable Logic DesignLine Blog  
10/24/2011   Post a comment
To date, Xilinx says that it’s shipped thousands of Virtex-7 and Kintex-7 FPGAs worldwide…
3D TSV Test: ATE challenges and potential solutions
Design How-To  
10/24/2011   2 comments
This paper presents some of the 3D TSV test challenges and proposes potential solutions for them; it also attempts to clarify some 3D TSV test myths and misconceptions…
Cadence CEO: Chip execs eye China, India
News & Analysis  
10/21/2011   6 comments
Lip-Bu Tan, chief executive at Cadence Design Systems, says semiconductor industry leaders spend a lot of time thinking about China and India, because those markets will see explosive growth in chip consumption.
What were they thinking: Bird watchers paradise
Blog  
10/21/2011   1 comment
For some fun this week, I have picked another patent. This time we look at a device for bird watching – up close and personal…
Wanted: Hexadecimal Nixie Tubes or similar display devices
Engineering Pop Culture!  
10/21/2011   14 comments
As usual I have an unusual hobby project simmering away on metaphorical stove…
Travel Nightmares: Was that crunching sound my notebook computer?
Blog  
10/21/2011   2 comments
…when suddenly, with a resounding “thunk” and associated “crunch”, my backpack hit the floor…
Book Review: The Artificial Ape by Timothy Taylor
Engineer’s Bookshelf  
10/20/2011   8 comments
I was taught that our ancient ancestors started to become more intelligent, which allowed us to start creating tools, but maybe things didn’t occur in quite this way…
According to George: The rules dont apply to us
Blog  
10/20/2011   4 comments
Can we build quality into the chip design process in the same way that the automotive industry did? Use less inspection (verification) and build in better quality…
Xilinx to demo Zynq-7000 EPP SW/HW development tools at ARM TechCon 2011
Programmable Logic DesignLine Blog  
10/20/2011   Post a comment
Hot news about the forthcoming ARM TechCon 2011 - I only wish I could attend myself, but...
How it was: Big computers talking to little computers
Programmable Logic DesignLine Blog  
10/19/2011   Post a comment
In the not-so-distant-past, computers of different types from different manufacturer could not typically "talk" to each other…
Holding the ancient past in the palm of your hand
Engineering Pop Culture!  
10/19/2011   31 comments
I cannot tell you what it feels like to hold something like a 4200-year-old Sumerian tablet; It sends shivers down my spine...
EDA/IP Weekly Roundup
Blog  
10/19/2011   Post a comment
There are often many news items that are not worth writing a full blog about, but may still be of interest to people. This is a roundup of those items…
Implementing high Speed USB functionality with FPGA- and ASIC-based designs
Design How-To  
10/18/2011   Post a comment
A wide range of FPGA-based applications exist that can benefit greatly from the addition of a high speed USB interface…
Opinion: Incentives for FPGA developers to change
Engineering Pop Culture!  
10/18/2011   1 comment
Lewis Sternberg thinks about why FPGA developers are slow to adopt ASIC verification practices and what may be changing…
Travel Nightmares: Flying into the old Hong Kong airport
Programmable Logic DesignLine Blog  
10/18/2011   5 comments
Flying into the original Hong Kong airport was an experience everyone remembers... especially if you had not been forewarned...
Oh, the irony!
The Engineering Life - Around the Web  
10/18/2011   5 comments
A friend just sent me an email containing a bunch of images that reflect life’s little ironies.
World’s first 1080p/30fps FPGA-based video analytics solution from Altera and Eutecus
Product News  
10/18/2011   2 comments
Single-chip solution performs video analytics at 1080p/30fps HD resolution for greater accuracy, detail, and flexibility
It takes three baby: Cadence, ARM and TSMC
News & Analysis  
10/18/2011   1 comment
A three way partnership between Cadence, ARM and TSMC has resulted in a 20nm test chip following an 18 month collaboration…
How it was: Testing honking big computers
Programmable Logic DesignLine Blog  
10/17/2011   4 comments
Once we had designed a new mainframe computer and build the prototype we had to test it…
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