Embedded Systems Conference
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Content tagged with Design Tools (EDA)
posted in October 2011
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Opinion: Is DV the ladder to nowhere?
Engineering Pop Culture!  
10/4/2011   9 comments
We all have opinions and they are a great way to get conversations started. Here is one from my friend Lewis Sternberg who believe that being in verification limits your future...
Swatch chip arm qualifies Bluetooth LE chip
Product News  
10/4/2011   4 comments
EM Microelectronic-Marin SA, the semiconductor division of the Swatch Group, has announced that its EM9301 Bluetooth low energy radio chip has received Bluetooth V4.0 qualification.
Machinarium – One of the most amazing computer games I’ve ever seen!
The Engineering Life - Around the Web  
10/3/2011   5 comments
I keep telling myself that I don’t play computer games, but I just realized that I’m currently devoting hours of my time to an amazing creation called Machinarium…
Oooohhhh, Shiny!!! The BMW i8 concept car
Engineering Pop Culture!  
10/3/2011   2 comments
I’m not usually much interested in cars, but in the case of the BMW i8 I will make an exception…
Springsoft becomes more open
Blog  
10/3/2011   Post a comment
When things become open, they tend to get used more and that is the primary intent for Springsoft as they open up access to the FSDB and KDB data…
How It Was: PCB Layout from Rubylith to Dot and Tape to CAD
Programmable Logic DesignLine Blog  
10/3/2011   9 comments
Dot and Tape refers to the product used to lay the patterns of tracks and IC/transistor pads on to mylar sheets; before Dot and Tape there was Rubylith...
Debunking the myth of the $100M ASIC
Blog  
10/3/2011   17 comments
A false belief that leading-edge chips cost up to $100 million to develop has severely decimated levels of venture capital investment in semiconductors, diminishing innovation.
Startup offers embedded memory IP
News & Analysis  
10/3/2011   1 comment
Memoir Systems Inc. is a 2009 startup company that has begun offering embedded memory intellectual property aimed at SoCs being designed for the networking and multicore processor markets.
Travel Nightmares: Lou Covey assumes a new identity
Blog  
10/3/2011   1 comment
Traveling can always mean problems and in our continuing series about travel nightmares, Lou Covey recounts one of his problematic journeys...
Reducing Turnaround Time with Hierarchical Timing Analysis
Design How-To  
10/3/2011   1 comment
STA is a key task during chip design that directly impacts design cycle time. Hierarchical techniques are used to break down design complexity into manageable units...
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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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