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posted in November 2001
Roadmap for chipmaking puts CMOS alternatives into mainstream
News & Analysis  
11/29/2001   Post a comment
The international committee working on the roadmap for the semiconductor industry for the next 15 years has decided to look at alternatives to conventional CMOS transistors as the brick wall that threatens the current approach to scaling looms closer.
Atmel says logic conversion blocks cut costs compared to FPGAs and CPLDs
News & Analysis  
11/21/2001   Post a comment
NANTES, France--Atmel Corp. here today announced new 0.25- and 0.35-micron embedded memory blocks for its Ultimate Logic Conversion products, which will enable users of field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) to move their designs to lower cost ULC-configured devices.
Taiwan confronts SoC obstacles
News & Analysis  
11/20/2001   Post a comment
IC design houses in Taiwan expect difficulties in quickly designing cost-effective system-on-chip products based on reusable intellectual property cores will be a key challenge as the island tries to become a provider of higher value products and services.
Synopsys, ARM create design flow for core licensees
News & Analysis  
11/19/2001   Post a comment
Synopsys Inc. and ARM Ltd. have jointly created an RTL-to-GDSII reference design flow in an effort to help ARM's semiconductor licensees quickly create and harden custom variations of the ARM946-S synthesizable processor core.
Fujitsu to use synthesizable 32-bit ARM cores in ICs for portable products
News & Analysis  
11/19/2001   Post a comment
TOKYO -- Fujitsu Ltd. today announced it has licensed two synthesizable, 32-bit RISC processor cores for use in integrated circuits inside portable multimedia products, such as digital cameras, personal digital assistants (PDAs), next-generation cell phones, and Internet appliances.
Altera, Synopsys plan 'ASIC-like' design solutions for complex PLDs
News & Analysis  
11/14/2001   Post a comment
SAN JOSE -- Altera Corp. and Synopsys Inc. today announced plans to jointly develop ASIC-like design solutions for complex system-on-programmable-chip (SoPC) devices. The partnership will address the need for next-generation design and verification flows for high-density programmable logic devices, said the two companies.
Synopsys acquires technology assets from C Level Design
News & Analysis  
11/12/2001   Post a comment
MOUNTAIN VIEW, Calif.--Synopsys Inc. today announced it has agreed to acquire technology assets from nearby C Level Design Inc., and it will integrate the company's CycleC simulation tool into its VCS simulator to accelerate HDL simulations.
Japanese tout simplified transistor design methodology
News & Analysis  
11/8/2001   Post a comment
The University of Hiroshima has teamed with Japan's Semiconductor Technology Academic Research Center (Starc) to unveil a transistor design methodology for both CMOS and analog-based circuits that they hope will replace the troubled BSIM4 method.
ITC 2001 Emphasizes More Cooperation, Less Test Cost
News & Analysis  
11/8/2001   2 comments
Activities and products at the recent International Test Conference focused on making manufacturing test faster and less expensive. Jim Lipman, TechOnLine's Content Director, discusses ITC's major themes along with some of the show's more interesting product announcements.
Mentor develops physical verification capabilities for IBM's SiGe process
News & Analysis  
11/7/2001   Post a comment
WILSONVILLE, Ore.--Mentor Graphics Corp. today announced it is developing physical verification tools for IBM Corp.'s silicon-germanium (SiGe) foundry processes and highly integrated mixed-signal ICs.
Do Legwork Before Making ASIC Move
News & Analysis  
11/6/2001   1 comment
Mentor's first wave of new FPGA synthesis tools targets 50 million gate designs
News & Analysis  
11/6/2001   Post a comment
WILSONVILLE, Ore. -- Three months after disclosing an ambitious plan to redefine design software for field programmable gate arrays, Mentor Graphics Corp. here is preparing to ship its first beta versions of knowledge-based, heuristic synthesis tools targeting next-generation FPGAs with up to 50 million ASIC gates on a chip.


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