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posted in November 2002
How Sun reduced cost /supply risk by moving to COT
News & Analysis  
11/25/2002   Post a comment
Last year engineers at Sun Microsystems began a project to source a limited number of ASIC devices through a customer-owned tooling (COT) model.
Designing a high-performance, low-cost switch fabric chip-set using COT
News & Analysis  
11/25/2002   Post a comment
Tau Networks recently announced a T64 switch fabric chipset consisting of two multi-million gate chips.
COT: post design considerations
News & Analysis  
11/25/2002   Post a comment
The proliferation of libraries and intellectual property (IP) in the customer-owned tooling (COT) world has lowered the barrier of entry for those interested in moving to a COT design flow.
COT versus ASIC
News & Analysis  
11/25/2002   Post a comment
COT or ASIC? No brainer for big, fast router market
News & Analysis  
11/25/2002   Post a comment
The router products market — where the average throughput growth is an incredible 2.2X every 18 months — is moving faster than the formidable Moore's Law.
ASIC to COT: knowing your outsourcing options
News & Analysis  
11/25/2002   Post a comment
The fabless model continues to grow as more companies recognize its benefits. The model includes both the customer-owned tooling (COT) and application- specific IC flows.
Packaging Choices for Wireless IC Designs
Design How-To  
11/22/2002   Post a comment
High-frequency chips pose difficult problems for designers looking for cost-effective, non-performance-limiting packages for these chips. Agilent's Chris Mueth discusses the different types of packages that are available, the required characteristics of these packages, and the need to integrate package and chip analysis into a common design flow.
Streamlining the SoC Design Flow
Design How-To  
11/20/2002   Post a comment
New process technologies are fueling ever-shrinking chips of rapidly increasing density and complexity. At the same time, SoC times-to-market are also shrinking. Mentor Graphics' Claudia Relyea describes the challenges facing SoC design teams along with some ideas for streamlining the chip-design flow.
PCB Design-Tool Progress Continues Slowly
Design How-To  
11/6/2002   Post a comment
Compared to chip design-tool development, advancements in the PCB design-tool arena are not very dynamic. TechOnLine's Jim Lipman discusses why he thinks PCB tool development is so slow and what PCB tool vendors need to do to address upcoming system-design problems.


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Max Maxfield

Creating New Faceplates for Antique Analog Meters
Max Maxfield
41 comments
I've currently got a couple of hobby projects on the go that feature the use of antique analog meters. For example, there's my Inamorata Prognostication Engine and its companion, the ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
11 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
11 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
45 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

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