FPGA configures DSP core in imaging app News & Analysis 11/21/2003 Post a comment When Intevac developed the embedded electronic systems for NightVista, a compact, high-performance, ultralow-light camera, the first approach was built around a Texas Instruments DSP.
FPGA algorithm tunes gray, color images Design How-To 11/21/2003 Post a comment For both gray-scale and color image applications in an FPGA, we have implemented block truncation coding (BTC), a lossy image-compression algorithm with proven value in applications that don't require exact reconstruction of the original image.
Design of Base I/O Libraries Design How-To 11/20/2003 Post a comment Cell libraries clearly play a critical role in IC design today. They serve as the fundamental building blocks for any new chip design. Most developers have chosen a standard cell library early in the design process, frequently based on which IC foundry they are working withand verified that the library works smoothly within their design flow.
IC-package co-design supports flip-chips News & Analysis 11/13/2003 Post a comment With the advent of flip-chip, packages and silicon can no longer be designed in isolation. In this article, Agere Systems researchers including J.C. Parker detail Agere's IC-package co-design methodology, and list capabilities still needed from EDA vendors.
Power board accelerates DVD reference designs Product News 11/13/2003 Post a comment Power Integrations' Design Accelerator Kit (DAK-32) features an energy efficient 20-watt power supply reference design that delivers sufficient peak output to start motors and spin up drives found in DVD players and recorders. It consumes 1 watt in the standby mode.
Real-Time OS available for Moto's MSC8102 DSP Product News 11/12/2003 Post a comment Enea Embedded Technology, (formerly OSE Systems) has begun to offer its OSEck real-time kernel and Illuminator development tools for Motorola's MSC8102 digital signal processor. The MSC8102 combines four StarCore SC140 cores running at speeds of up to 300 MHz with four Enhanced Filter Coprocessors.
Full-Wave EM Modeling for RF, Mixed-Signal IC Design Product News 11/10/2003 Post a comment Agilent Technologies introduced an addition to its RF Design Environment that offers full-wave electromagnetic modeling capability for RF and mixed-signal design from within Cadence Design System's Virtuoso platform. Agilent RFDE Momentum enables electromagnetic modeling to help engineers in the communications industry increase productivity and speed development of wireless and wireline products.
Online simulator eases DC/DC designs Product News 11/9/2003 Post a comment Intersil Corporation's online circuit simulation tool, iSim, eases DC/DC regulator designs built around ten of its most popular PWM controller ICs. Now part of the company's online Technical Design Center providing documentation, design resources and product information, iSim provides Bode plot analysis using a simple interactive "edit-in-place" schematic based on actual reference designs.
VHDL harmonic balance extensions model RF circuits News & Analysis 11/6/2003 Post a comment Harmonic Balance simulators offer engineers the ability to visualize the behavior of an RF transceiver circuit in the frequency domain. VHDL-AMS/FD is the extension to the popular hardware description language that supports harmonic balance simulation for frequency domain analysis. This Frequency Domain (FD) language extension provides the RF designer the capability to describe the wireless system top down from the architectural level to down to the transistors and non-linear circuit elements. F
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments