Design Exploration Tools Encourage More Creativity Product News 11/30/2004 Post a comment What if a design tool had the hooks and means to capture a design, but, also had an inherent functionality to encourage you to creatively iterate, or explore? Instead of doing design iterations to fix problems, iterations would be done to streamline the design.
Zuken upgrades discontinued PCB tool News & Analysis 11/30/2004 Post a comment Zuken isn't selling its Visula 7.0 PCB design suite to new customers, and is actively trying to get existing customers to migrate to its CR-5000 product but that didn't stop Zuken from announcing a significant upgrade to Visula 7.0 Tuesday (Nov. 30).
EDA-Jünger treffen sich in Dresden News & Analysis 11/26/2004 Post a comment Technische und wirtschaftliche Zukunftsaspekte der Electronic Design Automation (EDA) will die Branche auf dem dem 'edaForum 04' am 9. und 10. Dezember in Dresden diskutieren.
OpenAccess-Umstieg lohnt sich für Chipentwickler Product News 11/25/2004 Post a comment Der Umstieg auf die Datenbank OpenAccess bringt Chipentwicklern enorme Vorteile. Dennoch steckt dahinter eine knackige Herausforderung, die nicht auf die leichte Schulter genommen werden darf. Das empfehlen jedenfalls drei große Chiphersteller, die den Sprung ins kalte Wasser gewagt haben.
'Wrap' your cores to enable SoC test News & Analysis 11/24/2004 Post a comment Flat scan chains don't work well with multiple IP blocks. ARM's Teresa McLaurin (right) and Synopsys' Rohit Kapur show you how to test cores hierarchically, using "wrapper boundary registers" that isolate a core from the surrounding logic.
Chip2Nite upgrade promises design time reduction News & Analysis 11/24/2004 Post a comment Promising to reduce overall design time by at least 20 percent, startup Silicon Dimensions Inc. is announcing an updated release of Chip2Nite, an IC design tool that provides floorplanning, placement, analysis and optimization for logic designers.
LabVIEW now encompasses control design and simulation Product News 11/24/2004 Post a comment Instrumentation house National Instruments now has a suite of control-oriented design and simulation tools that extends the company's popular LabVIEW graphical development environment to the design, implementation, and test of control systems.
Upgraded tool speeds IC package analysis News & Analysis 11/23/2004 Post a comment Promising an enhanced ability to model the electrical characteristics of IC packages, Fluent Inc. has rolled out Icemax 2.0. The new offering may help prevent some of the packaging problems that have come to plague PCB designers.
Infineon grows its own --nanotubes Product News 11/23/2004 Post a comment Infineon Technologies achieved a breakthrough when researchers constructed the world's smallest nanotube transistor, with a channel length of only 18 nm. The most advanced transistors currently in production are almost four times this size.
Bluespec gets $4.5 million more in VC funding News & Analysis 11/19/2004 Post a comment SystemVerilog behavioral synthesis startup, Bluespec Inc. has secured $4.5 million of additional funding to support channel expansion and increased customer engagements, the company announced Friday (Nov. 19).
La jeune pousse SiNavigator redonne un coup de jeune au secteur de la CAO News & Analysis 11/18/2004 Post a comment La plupart des jeunes pousses du secteur de la CAO favorisent les outils de pointe. Les vétérans de l’automatisation de la conception électronique qui ont fondé Silicon Navigator Corp. (SiNavigator) ont une vision plus large, un modèle de gestion de « composant logiciel » qui pourrait changer la manière dont les sociétés de CAO gèrent leurs affaires.
Cadence geht gegen chinesische Raubkopierer vor News & Analysis 11/18/2004 Post a comment Mit abgespeckten Versionen seiner EDA-Tools will dr Softwarehersteller Cadence Design Systems gegen Raubkopien vorgehen, die in China zunehmend kursieren. Der EDA-Anbieter folgt damit Microsofts Beispiel: Seit kurzem bietet der Software-Riese aus Redmond in bestimmten Teilen Asiens eine Einfach-Ausgabe seines Betriebssystems an.
Cadence upgrades equivalency checker News & Analysis 11/17/2004 Post a comment Cadence Design Systems Inc. has released version 5.0 of its Encounter Conformal formal verification tool with newly added FPGA support, clock domain checking and advanced datapath verification.
Cadence chercher à enrayer le piratage chinois News & Analysis 11/17/2004 Post a comment Dans l’espoir d’enrayer le piratage croissant des outils de CAO en Chine, Cadence Design Systems Inc. cherche un moyen pour proposer des versions “désassemblées” de ses suites de conception. Cette initiative reflète des efforts similaires de la part de Microsoft Corp., lequel a commencé à vendre une version simplifiée de son système d’exploitation dans certaines régions de l’Asie.
Three ex-Intel execs join Fister at Cadence News & Analysis 11/16/2004 Post a comment If there was any doubt that Mike Fister runs Cadence Design Systems Inc., that ended Tuesday (Nov. 16). Cadence announced a new management team led by former Intel executives Jim Miller, Ajay Malhotra, and Craig Johnson, along with the replacement of general managers Lavi Lev and Ping Chao.
A practical view of ESL design News & Analysis 11/12/2004 Post a comment Confused about ESL? Mentor Graphics' Serge Leef identifies the various categories of ESL tools, and shows how they'll help enable 100 million gate chips.
SRC and SIA throw SoC design competition News & Analysis 11/12/2004 Post a comment The Semiconductor Research Corporation (SRC) and the Semiconductor Industry Association (SIA) are co-sponsoring a contest in which they will be awarding a total of $75,000 to North American universities whose students come up with the most novel, low power designs.
How Infineon implemented OpenAccess News & Analysis 11/12/2004 Post a comment Infineon greatly speeded up its mixed-signal design flow by porting tools to the OpenAccess database. Authors including Thomas Heiter (right) show how it was done, and provide some tips for others considering such a move.
Atmel, Mentor expand agreement News & Analysis 11/9/2004 Post a comment Atmel Corp. (San Jose), and Mentor Graphics Corp. (Wilsonville, Ore.), have announced a multi-year extension and expansion of an existing OEM agreement for advanced synthesis, simulation, and verification tools.
Giga Scale IC gets new CEO News & Analysis 11/8/2004 Post a comment IC prototyping tool startup Giga Scale Integration Corp. has appointed EDA and Semiconductor veteran Adam Traidman as its new president and CEO.
ICCAD keynoter calls for EDA to become more "aware" News & Analysis 11/8/2004 Post a comment Design tools need to become power aware, physically aware, manufacturing aware, signal integrity aware and test aware starting at the 90 nm node, said Texas Instruments Fellow, Peter Rickert, here Monday (Nov. 8) in his keynote at ICCAD 2004.
No size fits all for signal processing on FPGA News & Analysis 11/8/2004 Post a comment Dramatic advances in FPGA technology have resulted in devices that can be used in very high-performance signal-processing applications, with the latest "platform" devices supporting processing power that is hundreds or thousands of times greater than that of traditional programmable DSPs.
Relational physical design: no absolutes News & Analysis 11/8/2004 Post a comment Physical design for reuse remains stuck at the hard macro, which prevents intellectual property from being optimized to the target design or easily migrated to the next process generation.
True reuse moves well beyond recycling News & Analysis 11/8/2004 Post a comment Chip designers may question the hype over design reuse, insisting they've been reusing code for years. Probe a little deeper, and this reuse consists of taking a similar block and using it as a starting point or example for the next-generation design.
IP Reuse News & Analysis 11/8/2004 Post a comment Over the past few years, the notion of reusable hardware intellectual property has gone from concept to ideal to platitude. Designers have been bludgeoned to the threshold of submission by charts and graphs that clearly show that next year, their smallest design will be over 10 zillion gates, and that in order to finish in the required 11 weeks, they will have to reuse previously designed and verified IP blocks for 98.734 percent of that total.
CoWare upgrades SystemC-based SoC modeling tools News & Analysis 11/5/2004 Post a comment CoWare Inc. has released a significant revision of its SystemC-based ConvergenSC system-on-chip (SoC) design tools that it claims will enable faster modeling and debug of IP models, platform subsystems, and SoC designs in SystemC.
Managing leakage power at 90 nm and below News & Analysis 11/5/2004 Post a comment What causes leakage power, and what can you do about it? Synopsys authors including Barry Pangrle (right) examine that question and discuss techniques including cell swapping and power gating.
Monterey und Magma - Lektionen für Unternehmensgründer Blog 11/4/2004 Post a comment Die EDA-Anbieter Monterey Design Systems und Magma Design Automation wurden etwa gleichzeitig und mit ähnlich hohem Startkapital gegründet. Magma überlebte, Monterey nicht. Aus der Geschichte von Monterey und Magma lassen sich einige wichtige Lektionen für alle ableiten, die mit dem Gedanken spielen, eine eigene Firma zu gründen.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments