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Content tagged with Design Tools (EDA)
posted in November 2007
MATLAB-to-C translation, part 1: Pitfalls and problems
Design How-To  
11/29/2007   2 comments
Part 1 of this 3-part series looks at the basic problems of translating basic MATLAB functions to C.
Simulating and verifying complex, large-scale (big) analog/RF circuits using Spice tools
Design How-To  
11/28/2007   Post a comment
Compare traditional SPICE, Digital FastSPICE, and Analog FastSPICE for analysis of big analog/RF circuits
Altera presents new Nios II embedded evaluation kit
Product News  
11/27/2007   2 comments
New kit showcases FPGA design capabilities for embedded systems with design examples that highlight features such as hardware acceleration and remote hardware update.
Altium releases 3D PCB visualization
Product News  
11/26/2007   Post a comment
Altium has relased version 6.8 of its Designer product that included a new 3-D PCB visualization capability.
New partner for www.OpenCores.org
News & Analysis  
11/26/2007   Post a comment
Swedish ASIC/FPGA design company ORSoC has officially undertaken the mission to maintain and develop the OpenCores.org site.
Altium makes it 'real' for PCB/FPGA designers
Product News  
11/26/2007   Post a comment
Altium Designer 6.8 delivers 300 new features and enhancements, including real-time 3D PCB visualization and navigation.
eASIC, Tensilica ink IP deal
Product News  
11/26/2007   Post a comment
Fabless ASIC house eASIC Corp. has added Tensilica Inc. to its intellectual-property (IP) roster.
The Great EDA Cover-up
Design How-To  
11/26/2007   Post a comment
Functional verification is an art, or so we are told. New technologies emerge that inject a dose of science into the process and these can make the process more predictable, increase efficiency and lower overall verification costs. This article exposes problems with current coverage metrics being used and looks at some recent advances that can make them more objective.
IIT team proposes joint approach for testing large SoC designs
News & Analysis  
11/21/2007   Post a comment
Researchers at the Indian Institute of Technology have come up with a new approach for test engineers to balance the need handling test data compression and power consumption parameters in large SoC designs.
Slicing the Pie Differently
Blog  
11/20/2007   Post a comment
Much more to say about changing the EDA revenue model.
ARC decoder IP extends MP3 battery life
Product News  
11/20/2007   Post a comment
ARC International has started sampling an MP3 decoder core for its Sound Subsystem that operates at under 7 MHz and dissipates less than 0.46 mW of power.
Actel Libero IDE v8.1 features power analysis and power-driven layout
Product News  
11/19/2007   Post a comment
Battery-life estimator in Actel Libero IDE v8.1 provides valuable analysis for portable designers.
Avnet Electronics Marketing releases new Virtex-5 development kits
Product News  
11/19/2007   Post a comment
New development kits from Avnet Electronics Marketing support the LX50T, LX110T, SX50T, or SX95T Virtex-5 devices.
Actel's IDE enhanced by software from Verific Design Automation
News & Analysis  
11/19/2007   Post a comment
Verific's Verilog and VHDL parsers, analyzers, and elaborators integrated into Actel's Libero Integrated Design Environment (IDE).
Actel Libero IDE v8.1 Maximizes Power Efficiency
Product News  
11/19/2007   Post a comment
Actel's Libero v8.1 helps deisgners conserve power.
I Know What You Didn't Verify Last Summer!
Design How-To  
11/19/2007   Post a comment
This is the third part of an article based on a book by Hamilton Carter on Verification.
India to be engine of Synplicity R&D, CEO says
News & Analysis  
11/16/2007   Post a comment
Synplicity is to hold flat on staffing in almost all of its 20 facilities worldwide, except its Indian center in Bengaluru, which it says will be doing at least half of the company's R & D activities, if not more, in the next five years.
OneSpin Solutions expands in Japan
News & Analysis  
11/15/2007   Post a comment
Known for its formal verification solutions for ASIC and FPGA designs, OneSpin is expanding its business operations in Japan.
Optimized Mentor-MathWorks FPGA design flow
Product News  
11/15/2007   Post a comment
Mentor announces an optimized FPGA design flow between Precision Synthesis and MathWorks Simulink HDL Coder.
Mentor Integrates Precision Synthesis and Simulink HDL Coder from Mathworks
Product News  
11/15/2007   Post a comment
Mentor Graphics Precision Synthesis accept supports the Mathworks Simulink HDL Coder.
Book to celebrate ten years of DATE
News & Analysis  
11/15/2007   Post a comment
Organizers of the Design Automation and Test in Europe (DATE) conference are celebrating ten years of the event with a book that collates 30 of the best papers presented at the event since its inception.
Generate FPGA designs from M-code
Design How-To  
11/15/2007   Post a comment
You can use MATLAB M-files with the AccelChip synthesis tool to implement DSP on Xilinx FPGAs.
UnifiedLogic - a revolution in embedded system design
Design How-To  
11/14/2007   Post a comment
Imagine a futuristic embedded design environment -- in seconds you have access to a custom RTOS including drivers integrated with a hardware prototype -- believe it or not, it's here today!
IBM Selects Virtutech's Simulator for Power Architecture Ecosystem
News & Analysis  
11/14/2007   Post a comment
IBM selected Virtutech to create system-level models for future PowerPC chips.
Xilinx announce latest and greatest MicroBlaze 32-bit soft processor core (and lots more "stuff")
Product News  
11/14/2007   Post a comment
New MicroBlaze 7.00 from Xilinx boasts mega-cool features like an MMU that enables commercial-grade OS support.
Utilizing FPGA-based circuit emulation to reduce wireless backhaul costs
Design How-To  
11/14/2007   Post a comment
Users of IP cores can implement all key aspects of a circuit emulation system on a flexible and compact FPGA-based platform.
Windows CE marries embedded, Web services
Product News  
11/14/2007   Post a comment
Tomorrow's embedded systems will be access points for a growing array of network services, according to executives at Microsoft Corp. who are rolling out a new release of Windows CE software to help enable the shift as well as a new initiative to reach out more broadly to hardware developers as it competes with Linux to command a rising share of the embedded software market.
Altera's Nios II FPGA soft processor core now available for standard cell ASIC designs
Product News  
11/13/2007   Post a comment
As part of an Altera-Synopsys collaboration, the Nios II processor core is now available as a DesignWare Star IP offering.
New IP to simplify FPGA development
Product News  
11/13/2007   Post a comment
Online FPGA IPNet and I/O modules from NI and collaborators simplify FPGA development by provide measurement, control, and processing IP.
Configuration-based Environment that Supports Scalable PHY Verification
Design How-To  
11/13/2007   Post a comment
Leading-edge analog/mixed-signal design requires custom flows built with a variety of tools that use a multiplicity of design representations. When it is a centralized resource, a single verification team may be faced with overwhelming complexity when supporting multiple design teams, each with multiple tools and a variety of design representations.
Needed: A new design-to-fab flow for advanced ICs
Design How-To  
11/13/2007   Post a comment
As the increasing precision of hardware geometries pushes the limits of visible-light lithography, manufacturers' reliance on DRC and DFM checks can make the difference between manufacturable and nonmanufacturable designs.
HDL Designer Series Supports SystemVerilog
Product News  
11/13/2007   Post a comment
Mentor Graphics Corporation announced that its HDL Designer Series product has been extended to provide a platform for implementing SystemVerilog.
Second Class Citizens
Blog  
11/12/2007   Post a comment
The EDA industry must share not only the challenges, but also the rewards of a growing electronics industry.
What's going to be hot at SC07?
News & Analysis  
11/9/2007   Post a comment
This year's Supercomputing Conference (Nov 10-16 in Reno, NV) looks like being a bumper year for...
Software specialist FogClear focuses post-silicon
News & Analysis  
11/9/2007   Post a comment
FogClear, a software-only approach to post-silicon debugging, was unveiled this week by University of Michigan researchers at the international Conference on Computer-Aided Design.
Insights using NAND flash in portable designs
Design How-To  
11/8/2007   1 comment
As the raging success of Apple's iPod still rings in our ears, NAND flash memory is seen as the rising star of solid-state memory for portable and consumer applications.
The HDMI Design Guide: A short compendium for successful high-speed PCB design in HDTV receiver applications
Design How-To  
11/7/2007   Post a comment
This article presents design guidelines for helping users of HDMI mux-repeaters to maximize the device's full performance through careful printed circuit board (PCB) design. We'll explain important concepts of some main aspects of high-speed PCB design with recommendations.
Dynamically-reconfigurable Elemental Computing Arrays (ECAs) - Part 1 (Architecture)
Design How-To  
11/7/2007   Post a comment
ASICs, FPGAs, CPUs/DSPs, and SoCs have been joined by a new kid on the block - the Elemental Computing Array (ECA) from Element CXI.
FPGA-based simulator mimics CameraLink cameras
Design How-To  
11/6/2007   Post a comment
GiDEL announces an FPGA-based CameraLink camera simulator to speed development of vision and imaging systems.
The sky is not falling
Blog  
11/6/2007   Post a comment
The news that Mentor Graphics has downgraded the guidance for its quarter revenue has generated much talk in the EDA community, and people are busy trying to figure out if this is a signal of more fundamental changes in the industry.
Design with Verification: Not an Oxymoron
Design How-To  
11/6/2007   Post a comment
The article makes the case that while a dedicated verification team is essential at the cluster (multi-block) and chip levels, effective, efficient verification of large, complex chips must also involve the designers.
Synplicity's DSP Synthesis supports Lattice FPGAs
Product News  
11/5/2007   Post a comment
DSP algorithm implementation targets aerospace, wireless, telecom and digital multimedia applications.
Nanoscale chip verification: a massively analog problem?
News & Analysis  
11/5/2007   1 comment
As semiconductor manufacturing technology deals increasingly with finer and finer measurements, verification of nanoscale components presents a problem of scale, requiring a scaling of verification technology commensurate with the shrinking of technologies like CMOS.
CoWare Introduces ESL 2.0
News & Analysis  
11/5/2007   Post a comment
CoWare, Inc, announced the release of a major upgrade to all of its products line supporting companies in their transition from the proof-of-concept ESL era to ESL 2.0.
Coware releases major updates to its products line
Product News  
11/5/2007   Post a comment
In a major release of all of its ESL tools, Coware has pronounced a new era for ESL.
Kit accelerates Windows embedded CE 6.0 development
Product News  
11/4/2007   Post a comment
PHYTEC and Adeneo have teamed up to offer a low cost acceleration kit for Microsoft Windows embedded CE 6.0.
Challenges of clocking a high-definition world, (Part 1 of 2): Foundational concepts
Design How-To  
11/2/2007   Post a comment
Clocks and jitter affect all aspects of system performance, including SNR and throughput; understanding and implementing today's ever-higher-speed clocks is crucial
Innovative Integration delivers new PCI Express module
Product News  
11/2/2007   Post a comment
X5-210M module features four 14-bit 210 MSPS A/Ds with a Virtex5 FPGA computing core, DRAM and SRAM memory, and eight lane PCI Express host interface.
SPICE circuit simulator targets 1M transistor circuits
Product News  
11/1/2007   Post a comment
Berkeley Design Automation has introduced a 64-bit version of its Analog FastSPICE circuit simulator, which is said to deliver true SPICE accuracy on greater than 1 M transistor circuits.


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46 comments
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