The Great EDA Cover-up Design How-To 11/26/2007 Post a comment Functional verification is an art, or so we are told. New technologies emerge that inject a dose of science into the process and these can make the process more predictable, increase efficiency and lower overall verification costs. This article exposes problems with current coverage metrics being used and looks at some recent advances that can make them more objective.
India to be engine of Synplicity R&D, CEO says News & Analysis 11/16/2007 Post a comment Synplicity is to hold flat on staffing in almost all of its 20 facilities worldwide, except its Indian center in Bengaluru, which it says will be doing at least half of the company's R & D activities, if not more, in the next five years.
Book to celebrate ten years of DATE News & Analysis 11/15/2007 Post a comment Organizers of the Design Automation and Test in Europe (DATE) conference are celebrating ten years of the event with a book that collates 30 of the best papers presented at the event since its inception.
Windows CE marries embedded, Web services Product News 11/14/2007 Post a comment Tomorrow's embedded systems will be access points for a growing array of network services, according to executives at Microsoft Corp. who are rolling out a new release of Windows CE software to help enable the shift as well as a new initiative to reach out more broadly to hardware developers as it competes with Linux to command a rising share of the embedded software market.
Configuration-based Environment that Supports Scalable PHY Verification Design How-To 11/13/2007 Post a comment Leading-edge analog/mixed-signal design requires custom flows built with a variety of tools that use a multiplicity of design representations. When it is a centralized resource, a single verification team may be faced with overwhelming complexity when supporting multiple design teams, each with multiple tools and a variety of design representations.
The sky is not falling Blog 11/6/2007 Post a comment The news that Mentor Graphics has downgraded the guidance for its quarter revenue has generated much talk in the EDA community, and people are busy trying to figure out if this is a signal of more fundamental changes in the industry.
Design with Verification: Not an Oxymoron Design How-To 11/6/2007 Post a comment The article makes the case that while a dedicated verification team is essential at the cluster (multi-block) and chip levels, effective, efficient verification of large, complex chips must also involve the designers.
Nanoscale chip verification: a massively analog problem? News & Analysis 11/5/2007 1 comment As semiconductor manufacturing technology deals increasingly with finer and finer measurements, verification of nanoscale components presents a problem of scale, requiring a scaling of verification technology commensurate with the shrinking of technologies like CMOS.
CoWare Introduces ESL 2.0 News & Analysis 11/5/2007 Post a comment CoWare, Inc, announced the release of a major upgrade to all of its products line supporting companies in their transition from the proof-of-concept ESL era to ESL 2.0.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments