Awesome! Two amazing books for free! Blog 11/30/2010 14 comments Did you see my reviews of the books uC/OS-III The Real-Time Kernel by Jean Labrosse and uC/TCP-IP by Christian Légaré? Well, I just heard how you can get FREE copies of both these works…
Book Review: uC/TCP-IP by Christian Légaré Engineer’s Bookshelf 11/30/2010 2 comments I have to say that I am very, VERY impressed with the quality of books that are being written by the folks at Micriµm – the one I just finished reading on TCP-IP still has my head buzzing!
ESL, FPGAs, and configurability Blog 11/29/2010 1 comment Here’s a taxonomy for ESL and FPGAs that will hopefully prevent definitions from becoming as word- distorted and confused as they have become in so many other areas of EDA.
From RTL to GDSII in Just Six Weeks! Blog 11/29/2010 37 comments The amazing story of how one man single-handedly invented a new computing architecture, designed a multi-million-gate SoC, and went from RTL to GDSII tapeout in just six weeks.
Debug: More return for less clicks Blog 11/29/2010 6 comments The tremendous growth of the semiconductor industry over the past 40 years is in part attributed to advancements of the EDA industry that caters to chip design companies. Although most design steps have been automated, a significant aspect that still remains primitive is that of RTL debugging.
The evolution of design methodology Blog 11/24/2010 8 comments In nature, long periods of relatively stable environments are occasionally punctuated by large-scale changes that are the catalyst for evolution to create a large variety of mutations, and then for natural selection to weed out the unsuccessful ones. The environment in which design methodology lives is similar.
D&R readies Intelligent Project Architect Product News 11/24/2010 Post a comment Design & Reuse SA (D&R) has delivered Intelligent Project Architect (IPA) as part of its IP management platform. It is suitable for IP-based collaborative design project between geographically distributed teams using various revision control systems.
Case study: High-Level Synthesis – Ready for prime-time? Design How-To 11/24/2010 7 comments This article describes how TI implemented a Transaction-Level Model (TLM) based design and verification methodology utilizing Cadence C-to-Silicon Compiler on a Queue Manager design. It quantifies the results versus a traditional RTL-based methodology, highlighting both the benefits and remaining challenges of adopting a TLM design and verification flow utilizing C-to-Silicon Compiler.
IP in FPGAs: Blessing and a curse Blog 11/22/2010 12 comments With the IP-SoC 2010 event next week in Grenoble, we see FPGAs finally getting some kind of exposure. But, Dave Orecchio of GateRocket indicates that FPGA designers need to be aware of the unique nuances of using IP in these programmable platforms, and put in place tools and methodologies to overcome the IP use obstacles to success.
Technology waits for no one and nothing Blog 11/18/2010 2 comments Referring to the lyrics of "Time Waits for No One", co-written by Keith Richards and Mick Jagger of the Rolling Stones, Bob Smith of Magma explains that, in the world of electronics, technology waits for no one, especially IC developers or EDA suppliers.
Lynguent adds members to advisory board News & Analysis 11/17/2010 Post a comment Analog startup Lynguent Inc. said it has appointed Joe Agiato, president of Newlight Asset Partners, and Mike Hill, managing director of learning and organization development for Lam Research Corporation, to its advisory board.
Synopsys unveils DesignWare STAR ECC IP Product News 11/17/2010 3 comments Synopsys Inc. has delivered the DesignWare STAR ECC (Self-Test and Repair Error Correcting Codes) IP as part of its DesignWare STAR Memory product family to help reduce embedded memory transient errors.
New IC verification techniques for analog content Design How-To 11/17/2010 4 comments The amount of analog content increases as designers integrate more functions, such as WiFi, Bluetooth, 3G, GPS and audio. This article illustrates a number of analog design rules and how they can be verified efficiently. Verification requires technology that combines the circuit extraction capability of a traditional LVS tool, the geometric checks of a DRC tool, the ability to do selected parasitic extraction, and the ability to use analysis tools. This technology addresses problems that cannot
The Emperor of Ice-Cream Blog 11/16/2010 5 comments I just ran across a poem called The Emperor of Ice-Cream (it’s the author’s hyphen, not mine). If it hadn’t been explained to me I wouldn’t have a clue what it was about. Once you do know what it’s about, however, re-reading it really makes you think…
*Footprint Graphics* or *Land Patterns*? Blog 11/16/2010 9 comments OK, I know I’m supposed to spend my days pondering the imponderables pertaining to programmable logic, but FPGAs end up on circuit boards, and I just ran into a problem with regard to PCB terminology…
Oasys names VP of sales News & Analysis 11/10/2010 Post a comment EDA startup Oasys Design Systems Inc. said it has appointed Craig Robbins as senior vice president of sales, reporting to the company's CEO Paul van Besouw.
Parametric yield: Do you know what you miss? Design How-To 11/10/2010 Post a comment In today's technological complexity and constantly ROI demand, InfiniScale presents a model-based approach for process variability and yield enhancement of analog/mixed-signal and custom integrated circuits.
Electronica: CEO panel basks in upbeat mood News & Analysis 11/9/2010 Post a comment In the traditional CEO panel on the opening day of the Electronica exhibition, the participants were unanimous that the semiconductor industry handled the economic crisis of 2008-2009 well, and that the industry is now set fair for return to "normal" growth.
DAC co-locates with NASA/ESA conference News & Analysis 11/9/2010 Post a comment Interesting match. The 48th Design Automation Conference (DAC 2011) will be co-located with the 2010 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011), from June 6 to 9 2011, in San Diego, California, USA.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments