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posted in November 2010
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Falling IC development productivity means lost engineering jobs
11/30/2010   23 comments
Steadily declining IC development productivity means more job losses for engineers in the U.S. and Europe to their less expensive counterparts in second-world economies. And the trend is accelerating as chip design complexity outpaces gains in productivity.
QuickLogic’s DPO technology extends single-charge battery life by up to 36% in handheld devices
Product News  
11/30/2010   1 comment
Display Power Optimizer (DPO) technology from QuickLogic increases battery life in every system tested, regardless of form-factor or display size.
Awesome! Two amazing books for free!
11/30/2010   14 comments
Did you see my reviews of the books uC/OS-III The Real-Time Kernel by Jean Labrosse and uC/TCP-IP by Christian Légaré? Well, I just heard how you can get FREE copies of both these works…
Book Review: uC/TCP-IP by Christian Légaré
Engineer’s Bookshelf  
11/30/2010   2 comments
I have to say that I am very, VERY impressed with the quality of books that are being written by the folks at Micriµm – the one I just finished reading on TCP-IP still has my head buzzing!
ESL, FPGAs, and configurability
11/29/2010   1 comment
Here’s a taxonomy for ESL and FPGAs that will hopefully prevent definitions from becoming as word- distorted and confused as they have become in so many other areas of EDA.
From RTL to GDSII in Just Six Weeks!
11/29/2010   37 comments
The amazing story of how one man single-handedly invented a new computing architecture, designed a multi-million-gate SoC, and went from RTL to GDSII tapeout in just six weeks.
LatticeECP3 low-cost FPGA supports Broadcom HiGig protocol
Product News  
11/29/2010   1 comment
The folks at Lattice Semiconductor have just announced the immediate availability of the HiGig MAC IP core for their low-cost LatticeECP3 FPGA family.
Altium expands European team
News & Analysis  
11/29/2010   Post a comment
Altium Ltd. announced it has strengthened business activities across EMEA.
Debug: More return for less clicks
11/29/2010   6 comments
The tremendous growth of the semiconductor industry over the past 40 years is in part attributed to advancements of the EDA industry that caters to chip design companies. Although most design steps have been automated, a significant aspect that still remains primitive is that of RTL debugging.
Social media for engineers: good or garbage?
RF & Microwave Designline Blog  
11/28/2010   31 comments
Two weeks ago, I attended an EDAC panel session on Social Media for emerging companies to learn from the big guys.The insightful take-away… Engineers hate Twitter!
The evolution of design methodology
11/24/2010   8 comments
In nature, long periods of relatively stable environments are occasionally punctuated by large-scale changes that are the catalyst for evolution to create a large variety of mutations, and then for natural selection to weed out the unsuccessful ones. The environment in which design methodology lives is similar.
Synopsys unveils LightTools version 7.1
Product News  
11/24/2010   Post a comment
Synopsys Inc. has made enhancements to its LightTools illumination design and analysis software.
D&R readies Intelligent Project Architect
Product News  
11/24/2010   Post a comment
Design & Reuse SA (D&R) has delivered Intelligent Project Architect (IPA) as part of its IP management platform. It is suitable for IP-based collaborative design project between geographically distributed teams using various revision control systems.
Case study: High-Level Synthesis – Ready for prime-time?
Design How-To  
11/24/2010   7 comments
This article describes how TI implemented a Transaction-Level Model (TLM) based design and verification methodology utilizing Cadence C-to-Silicon Compiler on a Queue Manager design. It quantifies the results versus a traditional RTL-based methodology, highlighting both the benefits and remaining challenges of adopting a TLM design and verification flow utilizing C-to-Silicon Compiler.
Altera’s next-gen industrial networking, motor control, and safety solutions
Product News  
11/23/2010   1 comment
Good grief – it sounds like the place to be at the moment is the SPS/IPC/DRIVES 2010 Electric Automation Exhibition and Conference in Nuremberg, Germany,
Xilinx FPGA development platforms accelerate industrial system designs
Product News  
11/23/2010   3 comments
New industrial networking, machine vision and motor control platforms short-cut design and integration of hardware, software and IP for high-performance system-on-chip designs.
Book Review: uC/OS-III The Real-Time Kernel by Jean Labrosse
Engineer’s Bookshelf  
11/23/2010   11 comments
I've long wanted to know more about how a Real-Time Operating System (RTOS) performs its magic. The book µC/OS-III - The Real-Time Kernel explains all…
Creating industrial pump and fan applications with Altera FPGAs and Alizem motor-control IP
Design How-To  
11/22/2010   3 comments
How Altera’s FPGAs and Alizem’s motor control IP can be used to create industrial pump and fan control applications that result in increased performance, reduced cost, and faster time-to-market.
IP in FPGAs: Blessing and a curse
11/22/2010   12 comments
With the IP-SoC 2010 event next week in Grenoble, we see FPGAs finally getting some kind of exposure. But, Dave Orecchio of GateRocket indicates that FPGA designers need to be aware of the unique nuances of using IP in these programmable platforms, and put in place tools and methodologies to overcome the IP use obstacles to success.
Synopsys rolls DesignWare ARC processor core for Blu-ray Disc players
Product News  
11/19/2010   Post a comment
Synopsys Inc. has introduced the DesignWare ARC AS 221 BD dual-core processor and released enhancements to its DesignWare ARC 600 32-bit configurable processor family.
Very funny *Pitchman* video from Lattice Semiconductor
11/19/2010   2 comments
I just received an email from Brian Kiernan, who is the Corporate Communications Manager over at Lattice Semiconductor. Brian pointed me at a really funny video on YouTube.
Singapore's A*STAR joins EU research on molecular-sized processor chip
News & Analysis  
11/19/2010   1 comment
The A*STAR's Institute of Materials Research and Engineering (IMRE) partners ten European Union research organisations to work on the groundbreaking €10 million ATMOL project that lays the foundation for creating and testing a molecular-sized processor chip.
Technology waits for no one and nothing
11/18/2010   2 comments
Referring to the lyrics of "Time Waits for No One", co-written by Keith Richards and Mick Jagger of the Rolling Stones, Bob Smith of Magma explains that, in the world of electronics, technology waits for no one, especially IC developers or EDA suppliers.
Resurrecting the Cray-1 in a Xilinx FPGA
Design How-To  
11/17/2010   21 comments
Want a classic, mammoth, number-crunching supercomputer of your own? Why not build one? That’s what Chris Fenton did using a single Xilinx FPGA!
It’s crazy – Xilinx Virtex-7 FPGAs to support 2.78 terabits/sec!
Product News  
11/17/2010   5 comments
Xilinx have announced their forthcoming Virtex-7 HT family of devices, which will enable 100-400 Gbps applications and beyond – in a single FPGA – for next generation communication systems.
Lynguent adds members to advisory board
News & Analysis  
11/17/2010   Post a comment
Analog startup Lynguent Inc. said it has appointed Joe Agiato, president of Newlight Asset Partners, and Mike Hill, managing director of learning and organization development for Lam Research Corporation, to its advisory board.
Synopsys unveils DesignWare STAR ECC IP
Product News  
11/17/2010   3 comments
Synopsys Inc. has delivered the DesignWare STAR ECC (Self-Test and Repair Error Correcting Codes) IP as part of its DesignWare STAR Memory product family to help reduce embedded memory transient errors.
TSMC qualifies Synopsys' IC Validator for 40nm, 65nm
Product News  
11/17/2010   Post a comment
TSMC said it has qualified Synopsys' IC Validator physical verification tool for 40nm and 65nm interoperable DRC/LVS runsets.
Veridae integrates Verific's Verilog analyzer into Clarus
News & Analysis  
11/17/2010   Post a comment
Vancouver-based EDA startup Veridae Systems Inc. said it has licensed Verific's front-end software, Verilog Analyzer, for integration into its Clarus family of debug and validation products.
New IC verification techniques for analog content
Design How-To  
11/17/2010   4 comments
The amount of analog content increases as designers integrate more functions, such as WiFi, Bluetooth, 3G, GPS and audio. This article illustrates a number of analog design rules and how they can be verified efficiently. Verification requires technology that combines the circuit extraction capability of a traditional LVS tool, the geometric checks of a DRC tool, the ability to do selected parasitic extraction, and the ability to use analysis tools. This technology addresses problems that cannot
The Emperor of Ice-Cream
11/16/2010   5 comments
I just ran across a poem called The Emperor of Ice-Cream (it’s the author’s hyphen, not mine). If it hadn’t been explained to me I wouldn’t have a clue what it was about. Once you do know what it’s about, however, re-reading it really makes you think…
*Footprint Graphics* or *Land Patterns*?
11/16/2010   9 comments
OK, I know I’m supposed to spend my days pondering the imponderables pertaining to programmable logic, but FPGAs end up on circuit boards, and I just ran into a problem with regard to PCB terminology…
Are low power and FPGA an oxymoron?
11/16/2010   3 comments
FPGAs have a reputation for being power hogs, but does that mean that no battery operated device should use an FPGA? Not so fast on that...
Opal Kelly’s XEM6110 Spartan-6 FPGA module boasts External PCI Express
Product News  
11/16/2010   6 comments
This is jolly exciting, not the least that I personally hadn’t really heard about External PCI Express before now (there’s always something new to learn)…
FPGAs: System gates or logic cells/elements?
11/16/2010   8 comments
This is one of those questions that keeps on coming back to bite us. May 1,000 curses rain down on the heads of those marketing weenies who first came up with the concept of *System Gates*
Free Virtual Conference: System-on-Chip 2.0
11/15/2010   1 comment
I don’t know about you, but I’m started to get rather excited about the forthcoming SoC 2.0 Virtual conference, which is to be held on Thursday, November 18…
How to bang often many than vindicatory!
11/15/2010   12 comments
I just saw the funniest thing. It’s a blog about an interview with two guys I know, but it looks like it started off in English, was translated into Hindi, and then...
Facts and data versus heuristics and hope
11/15/2010   6 comments
In the next five years, many chip companies will be saddled with underperforming that persistently miss product development schedules.
FTDI unveils USB 2.0 development board
Product News  
11/12/2010   Post a comment
Future Technology Devices International Ltd. (FTDI) launched Vinculo, a development platform for embedded systems requiring USB 2.0 connectivity, at the Electronica exhibition.
Altium supports Microsemi’s SmartFusion mixed-signal FPGAs
Product News  
11/11/2010   1 comment
Altium will provide its Altium Designer software as an option to customers using Microsemi’s SmartFusion intelligent mixed signal FPGAs.
Altium to support Microsemi's SmartFusion
News & Analysis  
11/10/2010   1 comment
Design software vendor Altium will provide its Altium Designer software as an option to customers using SmartFusion intelligent mixed-signal FPGAs from Microsemi Corp.
EDA 'co-opertition'—a new era or more lip service?
Semi Conscious  
11/10/2010   4 comments
Cadence's chief marketing officer talked a big game about cooperation during the ARM Technology Conference, but is it just lip service?
To a poet a thousand years hence
11/10/2010   10 comments
Here’s a poem that I cannot get out of my head. I first saw it whilst on a trip to England this summer to attend my dear old mom’s 80th birthday…
Zocalo Tech forms technical advisory board, names EDA expert
News & Analysis  
11/10/2010   Post a comment
Texas-based EDA startup Zocalo Tech Inc. announced it has established a Technical Advisory Board (TAB) and appointed Brian Bailey, an EDA verification expert, as its first TAB member.
Oasys names VP of sales
News & Analysis  
11/10/2010   Post a comment
EDA startup Oasys Design Systems Inc. said it has appointed Craig Robbins as senior vice president of sales, reporting to the company's CEO Paul van Besouw.
Parametric yield: Do you know what you miss?
Design How-To  
11/10/2010   Post a comment
In today's technological complexity and constantly ROI demand, InfiniScale presents a model-based approach for process variability and yield enhancement of analog/mixed-signal and custom integrated circuits.
Low-power 6G CPRI v4.1 REC solution from eASIC and Radiocomp
Product News  
11/9/2010   1 comment
Combining eASIC’s Structured ASICs with Radiocomp’s IP, the power consumption of CPRI-based designs is reduced by up to 80%, with exceptionally high signal integrity compared to FPGA implementations.
An Electronica Compendium
News & Analysis  
11/9/2010   Post a comment
Gathered below are a number of our stories from the Electronica 2010 exhibition
Electronica: CEO panel basks in upbeat mood
News & Analysis  
11/9/2010   Post a comment
In the traditional CEO panel on the opening day of the Electronica exhibition, the participants were unanimous that the semiconductor industry handled the economic crisis of 2008-2009 well, and that the industry is now set fair for return to "normal" growth.
DAC co-locates with NASA/ESA conference
News & Analysis  
11/9/2010   Post a comment
Interesting match. The 48th Design Automation Conference (DAC 2011) will be co-located with the 2010 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011), from June 6 to 9 2011, in San Diego, California, USA.
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