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Content tagged with Design Tools (EDA)
posted in November 2010
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The company formally known as Actel unveils 65nm embedded flash platform
Product News  
11/8/2010   2 comments
I shouldn’t poke fun, because this is a very interesting announcement, but I really find it hard to say Microsemi’s SOC Products Division, formerly known as Actel Corporation…
New Lattice MachX02 is the Do-It-All PLD
Product News  
11/8/2010   3 comments
65nm MachX02 PLDs deliver 3X increase in logic density, 10X increase in embedded memory, more than a 100X reduction in static power, 30% lower cost compared to their predecessors.
I want a Pico Projector … but which one?
11/8/2010   11 comments
It’s funny… I had vaguely been aware of Pico Projectors for quite some time, but I hadn’t realized that they were actually available and (sort of) affordable – now I want one!
FPGAs pave the way for consumer-targeted PICO projectors
Design How-To  
11/8/2010   2 comments
A new type of portable video projector – commonly called Pico Projectors – that can fit in the palm of the hand is rapidly growing in popularity with business professionals.
Dolphin Integration rolls test solution for embedded memories
Product News  
11/8/2010   Post a comment
Dolphin Integration has launched the HD BIST (Built-In-Self-Test) as part of its High Density – Low Power Panoply of silicon IPs.
Samsung adopts Arteris for mobile chips
News & Analysis  
11/8/2010   1 comment
Arteris Inc., a licensor of network-on-chip interconnect intellectual property, has said that consumer electronics giant Samsung Electronics Co. Ltd. has selected its IP for mobile system-on-chip ICs.
Power Tip 29: Estimating transient temperature rise in a hot-swap MOSFET–Part 2
Design How-To  
11/7/2010   2 comments
Understand a simple technique to estimate this critical application parameter
How complex is your chip design?
11/6/2010   Post a comment
When planning new IC design projects, such as SoCs or complex analog or RF chips, R&D organizations that have a firm grasp on the complexity of implementing the design wield a powerful competitive advantage.
These videos will make you laugh your socks off…
11/5/2010   3 comments
Here are some mega-funny videos, such as the one about the Rockwell Retro Encabulator, which is absolutely brilliant (how the presenter keeps a straight face I will never know)!
Having fun with programmable logic
11/5/2010   1 comment
You know how I often say ‘Have you done anything interesting recently with CPLDs or FPGAs or any other form of programmable logic? If so please tell me about it.’ Well someone did…
How to have fun with the Lattice XP2 development board
Design How-To  
11/5/2010   1 comment
A small group of engineers were asked to put together some “science fair” type projects that would show their families some aspects of the work accomplished at Sparton Defense and Security Systems.
MathWorks' tools cut satellite GNC systems development time by 50%
News & Analysis  
11/5/2010   Post a comment
MathWorks said Swedish Space Corporation (SSC) has licensed Model-Based Design with MATLAB and Simulink to develop advanced autonomous formation flying software.
Windows 7 – Office 2010 – Visio 2010 – Arrggh!
11/4/2010   1 comment
In which I come to grips with the ups and downs of migrating to Windows 7, Office 2010, Visio 2010, and a number of other applications that make my eyes water and my lower lip quiver…
Will IP use increase in forthcoming SoC design?
11/4/2010   2 comments
If you wonder why SoC designers have such a nightmare using IPs delivered by 3rd parties, Piyush Sancheti of Atrenta highlights a few issues.
Docea Power successfully bootstraps as a new EDA player
The Entrepreneurial Engineer  
11/4/2010   Post a comment
I had a chance to catch up with Ghislain Kaiser, CEO of Docea Power, a promising new startup based in France.
New Computer – Windows 7 – Office 2010 – Eeeek!
11/3/2010   3 comments
Due to an unfortunate sequence of events, I had only one day available to purchase a new computer and some core application software packages; this then is the tale of that fateful day…
Mentor and ARM link for memory test
News & Analysis  
11/3/2010   Post a comment
Mentor Graphics Corp. is working with ARM to provide an automated memory test and repair solution for ARM embedded memories and processor cores. Interoperability has been established between Mentor Graphics Corp.’s Tessent memory test and repair solution and ARM’s family of cores and embedded memory IP.
EDA start-up puts 'design for debug' in the lexicon
11/2/2010   1 comment
EDA startup Veridae Systems announced a tool to bring automation and a single user interface to SoC debug.
New PCI Express Root Complex (RC) Lite solution for Lattice FPGAs
Product News  
11/2/2010   1 comment
Lattice Semiconductor today announced the immediate availability of the PCI Express Root Complex (RC) Lite solution based on the LatticeECP3 and LatticeECP2M FPGA families.
Imagination to support CellMath on PowerVR
Product News  
11/2/2010   Post a comment
Imagination Technologies Group plc has signed an agreement with Forte Design Systems Inc. to extend its use of CellMath Optimizer EDA tool with current generation PowerVR graphics cores and to allow Imagination to distribute and support the design software.
EDA startup targets debug, validation
News & Analysis  
11/1/2010   Post a comment
An EDA startup spun out of research at the University of British Columbia came out of stealth mode promising to deliver a breakthrough technology for post-silicon debug and validation.
Emulator, accelerator, prototype – what’s the difference?
11/1/2010   3 comments
In a previous blog Brian talked about what makes a prototype unique, and said he would come back to the issue of emulators and accelerators… so here he is...
A next-gen FPGA-based SoC verification platform
Design How-To  
11/1/2010   6 comments
Off-the-shelf and custom FPGA-based prototype boards enhanced with co-emulation and co-simulation capabilities can provide a high-speed, high-visibility platform for fast, early verification of SoCs.
Veridae Systems delivers new debug solution for FPGAs, ASICs, and SoCs
Product News  
11/1/2010   1 comment
Silicon debug and validation suite provides on-chip visibility from multiple-FPGA ASIC prototypes through to final IC thereby reducing overall complex IC development time by 10 to 30%
Achronix’s next-gen FPGAs in Intel’s 22nm process
Product News  
11/1/2010   1 comment
Next-generation FPGAs from Achronix are to be built using Intel’s 22 nm process; the Speedster22i will be the first commercial FPGA family to have an end-to-end supply chain within the USA.
Ricoh uses DeFacto's DFT tool for complex designs
News & Analysis  
11/1/2010   Post a comment
Ricoh Company Ltd. said it has licensed the HiDFT-SIGNOFF Design-for-Test (DFT) solution from France-based EDA startup DeFacTo Technologies SA and reduced turnaround time during DFT process.
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