DAC co-locates with NASA/ESA conference News & Analysis 11/9/2010 Post a comment Interesting match. The 48th Design Automation Conference (DAC 2011) will be co-located with the 2010 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011), from June 6 to 9 2011, in San Diego, California, USA.
New Lattice MachX02 is the Do-It-All PLD Product News 11/8/2010 3 comments 65nm MachX02 PLDs deliver 3X increase in logic density, 10X increase in embedded memory, more than a 100X reduction in static power, 30% lower cost compared to their predecessors.
Samsung adopts Arteris for mobile chips News & Analysis 11/8/2010 1 comment Arteris Inc., a licensor of network-on-chip interconnect intellectual property, has said that consumer electronics giant Samsung Electronics Co. Ltd. has selected its IP for mobile system-on-chip ICs.
How complex is your chip design? Blog 11/6/2010 Post a comment When planning new IC design projects, such as SoCs or complex analog or RF chips, R&D organizations that have a firm grasp on the complexity of implementing the design wield a powerful competitive advantage.
Having fun with programmable logic Blog 11/5/2010 1 comment You know how I often say ‘Have you done anything interesting recently with CPLDs or FPGAs or any other form of programmable logic? If so please tell me about it.’ Well someone did…
Mentor and ARM link for memory test News & Analysis 11/3/2010 Post a comment Mentor Graphics Corp. is working with ARM to provide an automated memory test and repair solution for ARM embedded memories and processor cores. Interoperability has been established between Mentor Graphics Corp.’s Tessent memory test and repair solution and ARM’s family of cores and embedded memory IP.
Imagination to support CellMath on PowerVR Product News 11/2/2010 Post a comment Imagination Technologies Group plc has signed an agreement with Forte Design Systems Inc. to extend its use of CellMath Optimizer EDA tool with current generation PowerVR graphics cores and to allow Imagination to distribute and support the design software.
EDA startup targets debug, validation News & Analysis 11/1/2010 Post a comment An EDA startup spun out of research at the University of British Columbia came out of stealth mode promising to deliver a breakthrough technology for post-silicon debug and validation.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...