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Content tagged with Design Tools (EDA)
posted in December 2001
Mentor extends offer for IKOS, says it owns 9% of stock
News & Analysis  
12/26/2001   Post a comment
WILSONVILLE, Ore. -- Mentor Graphics Corp. today (Dec. 26) extended its unsolicited cash takeover offer for IKOS Systems Inc. until midnight Jan. 25, New York time, because it wants to give the Federal Trade Commission (FTC) more time to review the proposed purchase and merger.
Cadence to invest $50 million in China to expand design automation business
News & Analysis  
12/18/2001   Post a comment
BEIJING--Cadence Design Systems Inc. today announced it will invest $50 million in China to enhance its sales, support, and services for electronic design automation in the country's booming EDA market.
Formal verification link goes through Verisity language
News & Analysis  
12/17/2001   Post a comment
French design automation company TNI-Valiosys has licensed Verisity's e verification language as part of a project to link formal verification techniques with traditional simulation-oriented design checks.
SVR partnership yields lower-priced ASIC tools
News & Analysis  
12/14/2001   Post a comment
Silicon Valley Research Inc. has partnered with an unnamed ASIC synthesis tool company to offer an ASIC synthesis place and route combination priced below $100,000.
Antitrust concerns could delay Synopsys' purchase of Avanti
News & Analysis  
12/14/2001   Post a comment
Legal firms representing investors have voiced concerns that Synopsys Inc.'s bid to buy Avanti Corp. may raise antitrust issues with the Federal Trade Commission.
Circuit Semantics says new design analysis tools support customization
News & Analysis  
12/13/2001   Post a comment
SAN JOSE -- Circuit Semantics Inc. today announced new features and an option to its IC-design timing and characterization software, which are aimed at allowing users to customize tools by an application program interface.
How to verify ADSL chips
Design How-To  
12/13/2001   Post a comment
Asymmetric digital subscriber line technology, delivering more than 100 times the performance of today's analog modems, is revolutionizing the market for remote access devices.
Modular ASICs ease test problems
Design How-To  
12/13/2001   Post a comment
The largest FPGAs available today can implement close to 1 million (real ASIC) logic gates.
Testing mixed-signal Bluetooth designs
Design How-To  
12/13/2001   Post a comment
The Holy Grail: Create a Bluetooth system-on-chip (SoC) that fully integrates processor, programmable logic, SRAM, EEPROM and the RF transceiver for less than $5.
Coverage analysis essential in SoC design
Design How-To  
12/13/2001   Post a comment
Coverage analysis is as easy to adopt and integrate as it is essential to ensuring consistent, high-quality verification results.
Assertions speed processor core verification
Design How-To  
12/13/2001   Post a comment
Most of today's complex system-on-chip devices contain embedded processors; indeed some analysts insist that a chip must contain a processor even to qualify as an SoC.
Memory subsystems called 'next challenge' for system designers
Design How-To  
12/13/2001   Post a comment
Networking has benefited from advances in system-on-chip design, notably in terms of specialized intellectual property including network processors and on-chip buses.
ATE struggles to keep pace with VLSI
News & Analysis  
12/13/2001   Post a comment
The cost of testing complex system-on-chip designs will soon surpass the cost of manufacturing them.
Dense wires snarl verification plans
News & Analysis  
12/13/2001   Post a comment
Deep-submicron silicon technology makes it possible to implement increasingly complex system-on-chip designs, but it is also introducing new design and verification challenges.
Electromagnetic-Compatibility Analysis Using TEM Cells
News & Analysis  
12/10/2001   Post a comment
Transverse-electromagnetic (TEM) cells are important structures for analyzing the electromagnetic compatibility (EMC) of electronic components. Kresimir Malaric of University of Zagreb, Croatia discusses the design and analysis of several types of TEM cells available for emission testing of small equipment, calibration of RF probes, and biomedical experiments.
Mentor offers to buy IKOS for $102 million in move to block Synopsys
News & Analysis  
12/7/2001   Post a comment
WILSONVILLE, Ore. -- Mentor Graphics Corp. here today announced an unsolicited offer to acquire IKOS Systems Inc., a supplier of design verification technology, for $102 million in cash. San Jose-based IKOS had agreed in the summer to be acquired by Synopsys Inc. in a deal that is not expected to close until August 2002 (see July 2 story).
LogicVision strikes alliances to extend embedded test capabilities
News & Analysis  
12/5/2001   Post a comment
SAN JOSE -- LogicVision Inc. here has struck a couple of design-automation partnerships to expand the use of embedded test technology, including an agreement with Atrenta Inc. enable validation of test requirements early in IC development.
Synopsys to acquire Avant in all-stock EDA deal
News & Analysis  
12/4/2001   Post a comment
In the largest and most strategically significant acquisition in EDA history, Synopsys will acquire Avant. Mutual customers of the companies were pushing for the acquisition, said Aart de Geus, president and CEO of Synopsys.
Synopsys to acquire Avanti for nearly $780 million in stock
News & Analysis  
12/3/2001   Post a comment
MOUNTAIN VIEW, Calif.--Synopsys Inc. today announced an agreement to acquire Avanti Corp. for nearly $780 million in stock. Synopsys said it will exchange 0.371 of its shares for each outstanding share of Avanti under the agreement.


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michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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