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posted in December 2002
SoC: IP Reuse
Design How-To  
12/19/2002   Post a comment
Closing the abstraction gap in 100M-gate designs
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12/19/2002   Post a comment
One-hundred-million gates. One-billion transistors.
Verification reuse enables design reuse
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12/19/2002   Post a comment
We all know that design reuse is a critical element in closing the SoC design gap. Designers learned years ago that reinventing every new chip from scratch is not a scalable approach.
The five facets of SoC design complexity
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12/19/2002   Post a comment
"Digital convergence" is creating demand for functionally complex ICs in six-nine month design cycles at mass-market costs.
Re-use versus re-synthesize: Preparing for deep submicron issues ahead
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12/19/2002   Post a comment
Reuse today is largely focused on platform-based design which emphasizes the reuse of large blocks of fixed hardware configurations, pre-engineered for speed or power, with design flexibility effectively available only through software modification.
Layout compaction accelerates SoC design through hard IP reuse
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12/19/2002   Post a comment
In enabling multimillion-gate SoC designs, the latest process technologies have widened the gap between manufacturing capabilities and designers' abilities to quickly put together these complex devices.
7 warning signs that you should be concerned about your IP provider
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12/19/2002   Post a comment
Reusing semiconductor intellectual property (SIP or IP) blocks is no longer a luxury for the designers of complex chips — it is a necessity. As mask costs skyrocket and qualified engineering resources become increasingly scarce, chip design teams are incorporating IP reuse strategies into virtually every chip development plan in order to minimize design cycles, reduce chip respins, and meet time-to-revenue goals.
Your IP: easy to protect, easy to reuse
News & Analysis  
12/19/2002   Post a comment
Design engineers are constantly faced with the problem of creating and protecting intellectual property (IP) in new products.
High-speed fabrics deliver optimal IP implementation
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12/19/2002   Post a comment
When developing a customizable silicon architecture, one of the most important and most often overlooked aspects is developing a technology strategy to manage IP before the silicon details are frozen.
Analog IP re-use: concerns for "digitally-oriented" SoC designers
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12/19/2002   Post a comment
The topic of analog, mixed-signal, and radio frequency IP design for import into and re-use in ASIC and SoC chips, has been discussed at technical conferences and in industry magazines over the last few years.
Nanometer scale effects complicate IP characterization
News & Analysis  
12/19/2002   Post a comment
To meet the growing demand for higher performance applications, SoC designers are integrating increased numbers of larger memory IP blocks on more complex devices.
Synthesizable IP: the risk pays off
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When preparing to design our next-generation DVD controller, Amlogic's engineers faced a choice in design methodology.
Vendors must support IP reuse in SoC
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The ASIC industry was born out of the need of systems companies to achieve product differentiation, time-to-market advantage and cost optimization.
Flexible, standards-based IP key
News & Analysis  
12/19/2002   Post a comment
With the arrival of platform-based systems-on-chip and the proliferation of embedded cores, designs are getting bigger and more complex.
IP strategies proliferate as SoC complexity grows
News & Analysis  
12/19/2002   Post a comment
Merging previously designed circuit blocks into new system-on-chip designs seems like a sound way of controlling the complexity of SoC projects and leveraging the relatively scarce resources of the circuit design community — at least on the surface. But reuse of intellectual property (IP) is shaping up as a complex design approach with its own unique characteristics.
Taking the Frustration Out of Embedded Design
News & Analysis  
12/11/2002   Post a comment
Effective hardware/software co-design tools remain elusive for most embedded-system designers. Xilinx's Rich Sevcik discusses why he thinks emerging FPGA design platforms offer a viable alternative to ASIC-based embedded design.


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