Achieving signal integrity for ASICs, PCBs and packages News & Analysis 12/19/2003 Post a comment High-speed designs are causing signal-integrity problems in ASICs, packages and boards. In this tutorial, LSI Logic engineer David Chase shows you how to avoid problems due to reflections, crosstalk, noise, simultaneous switching outputs, IR drop, and voltage droop.
Open-source planning tool helps make live voice-quality measurements Product News 12/19/2003 Post a comment Here's news of an open-source add-on tool for making meaningful voice quality measurements on all kinds of telephony gear---both wired and wireless.
Used during the design phase of a product, it can yield margin by avoiding customer-related issues in the field. It can also help you evaluate voice network performance.
ADI broadens software tools line for DSPs Product News 12/19/2003 Post a comment Analog Devices, Inc. is beefing -up its line of software tools for its DSPs with the launching monday Dec. 22 of USB-based emulators and the VisualDSP++ integrated development and debugging environment (IDDE) release 3.5.
Analog CMOS supports precision specs News & Analysis 12/18/2003 Post a comment Many new portable applications call for higher levels of integration and low power, along with highly integrated digital and analog electronics, requiring low-power electronics to extend battery life and reduce device size.
CB process supports consumer amplifiers News & Analysis 12/18/2003 Post a comment Today the market for high-speed analog ICs is growing rapidly because of the ever-increasing demand for bandwidth. High-bandwidth amplifiers are finding such applications as xDSL and cable modems, set-top boxes, contact image scanners, DVD players and CD-ROMs.
High-speed op amps built using SiGe News & Analysis 12/18/2003 Post a comment High-performance applications such as third-generation wireless basestations and measurement and medical equipment demand faster response times from high-speed, high-resolution data converters and the amplifiers used to drive them.
Nanometer IC routing requires new approaches News & Analysis 12/12/2003 Post a comment What's the difference between gridded, shape-based, and graph-based routers? How do interconnect delays and signal integrity impact routing? Cadence Design Systems' David Desharnais answers these questions in this look at nanometer routing challenges.
Passive integration activates wireless Product News 12/10/2003 Post a comment Ron Wood of Atmel Corp. and Sotiris Bantas of Helic SA reveals why it has become important to understand the impact the package has on silicon circuits and to integrate an EDA tool into a foundry design kit in order to optimize both on-chip and in-package passives.
Start thinking out of known 'design box' News & Analysis 12/8/2003 Post a comment Recent major innovations in packaging technology have led to a number of more powerful and more flexible packages that attempt to cope with the challenges posed by designs containing multimillion gates and multigigahertz systems-on-chip.
Passive integration activates wireless News & Analysis 12/8/2003 Post a comment The wireless-design community has placed increased pressure on CMOS and BiCMOS foundries to combine multiplatform design environments into a single one to support both silicon and packaging co-design.
Write your own PCB database translator News & Analysis 12/6/2003 Post a comment If you ever have to move PCB placement files from one CAD system to another, you can write a simple translator using Perl. Luke Chang, verification engineer at Intel, shows how it's done in this step-by-step tutorial.
Accord helps EEs model non-linear, microwave, RF devices Product News 12/3/2003 Post a comment Instrument supplier Anritsu is teaming up with EDA supplier Modelithics to give developers the ability to do characterization of frequency-translating devices such as microwave mixers, up- and down-converters, and frequency multipliers. Characterization of devices working at frequencies as high as 40-GHz is possible.
'Best practices' improve hierarchical design constraints Design How-To 12/1/2003 Post a comment Setting the right physical and timing constraints is crucial for deep submicron ICs, especially with hierarchical design. In this article, Vijay Gullapalli from Synopsys Professional Services shows you "best practices" for managing constraints in hierarchical flows.