Cool EDA offerings for the new year News & Analysis 12/30/2004 Post a comment FPGA programming, easy formal verification, a video processing tool, Matlab-to-RTL, and FPGA-based emulation these are some of the recent developments that can help designers in 2005.
Top ten EEdesign stories of 2004 News & Analysis 12/30/2004 Post a comment From the legal troubles of ex-Aptix CEO Amr Mohsen, to Cadence Design Systems' new CEO and Synopsys' acquisition of Monterey Design Systems, here are the top ten EEdesign news stories of 2004, ranked according to reader response.
Aldec blends SystemC, HDL debugging News & Analysis 12/28/2004 Post a comment Expanding its capabilities for mixed-language simulation of ASICs and FPGAs, Aldec Corp. this week (Dec. 27) announced the release of Riviera 2004.12. New features include integrated SystemC and HDL debugging, assertion-based verification, and functional code coverage.
An introduction to PLM for EDA Design How-To 12/28/2004 Post a comment A chip development project may involve over 100,000 design files, says MatrixOne's Brad Hafer (right). He shows how product lifecycle management (PLM) can cut through the confusion, and describes how PLM can be tailored for EDA environments.
Sun, Cadence partner with Indian firm for VLSI training News & Analysis 12/28/2004 Post a comment Sun Microsytems and Cadence Design have partnered with Veda Institute of Information Technology, based in Hyderabad in southern India, to start the country's first nodal center of competency for research and development in VLSI engineering, design automation and embedded system engineering
Synopsys shift caused EDA decline, analysts say News & Analysis 12/23/2004 Post a comment A move by Synopsys towards subscription licenses was the primary reason for the EDA industry's revenue decline in the third quarter of 2004, according to two analysts. Meanwhile, the analysts said, the combined market share held by the "big three" EDA vendors is declining.
JTAG targets production test Product News 12/22/2004 Post a comment Working with JTAG? Here's a new software add-on that gives you a graphical way to run JTAG tests in production-line settings. Use it to test boards with JTAG-compatible devices on-board, such as BGAs, chip-scale packages, flip-chips, and other high-density packages.
EDA revenues decline in third quarter News & Analysis 12/22/2004 Post a comment A falloff in North American revenues resulted in a 3 percent decline in EDA license and maintenance revenue in the third quarter of 2004, according to the EDA Consortium's Market Statistics Survey (MSS). "The recovery is yet to come," said Wally Rhines, EDA Consortium chairman.
Mentor adds tools for flex PCBs Product News 12/21/2004 Post a comment Noting the increasing use of flex PCBs in applications requiring small form factors, Mentor Graphics Corp. has incorporated flex and rigid-flex PCB design capabilities into its Expedition and Board Station layout tools.
Philips, Spirit exec joins VSI Alliance's board News & Analysis 12/20/2004 Post a comment The Virtual Socket Interface Alliance, the intellectual property standards body, has continued its restructuring by recruiting to its board a Philips Semiconductor's standards guru and Spirit consortium Chairman Ralph Von Vignau.
Mixed-level modeling allows IC virtual prototypes News & Analysis 12/16/2004 Post a comment Electronic system level (ESL) design is necessary for complex SoCs, but how can you make it happen? Authors including Synopsys' Markus Wloka (right) present a dynamic mixed-level modeling methodology that lets you build virtual prototypes with functional models and detailed timed models.
RF tool vendor Eagleware buys ESL tool vendor Elanix News & Analysis 12/16/2004 Post a comment Privately held RF and microwave PCB design tool firm Eagleware Corp. (Norcross, GA) has signed a definitive agreement to purchase the assets of electronic-system level (ESL) design tool provider Elanix Inc. (Westlake Village, Calif.) for an undisclosed sum.
Synopsys and Agilent intro scan diagnostics Product News 12/15/2004 Post a comment Test-and-measurement giant Agilent Technologies and EDA/signal integrity powerhouse Synopsys announce an industry-first scan diagnostics reference methodology. According to the two firms, the new methodology will speed semiconductor fault localization and failure analysis by implementing bi-directional information sharing.
Labat leaves CEO position at TeraSystems News & Analysis 12/15/2004 Post a comment EDA provider TeraSystems Inc. is looking for a new CEO following the departure of Alain Labat from that position, EE Times has learned. TeraSystems provides silicon virtual prototyping tools for RTL handoff.
On-chip trace and debug approach targets Atmel FPGAs Product News 12/14/2004 Post a comment The domain of on-chip testability and debug continues to get better. Hardware verification and debug supplier First Silicon Solutions is teaming up with chip maker Atmel to jointly produce a product for on-chip debug, trace, and logic analysis of Atmel's popular FPSLIC and FPGA products.
Former 0-In CEO to head Summit Design News & Analysis 12/7/2004 Post a comment Preparing for a possible initial public offer (IPO), electronic system level (ESL) provider Summit Design Inc. has named EDA veteran Emil Girczyc as its new president and CEO. Girczyc was president and CEO of 0-In Design Automation prior to its acquisition by Mentor Graphics Corp. last June.
Low-cost Spice program adds features News & Analysis 12/6/2004 Post a comment new version of B2 Spice A/D from Beige Bag Software adds a redesigned user interface, new virtual instruments, and cross-probing between schematics and simulation. But what may be most attractive to many prospective users is the price, which starts at $249.
Dataquest issues 2004 EDA market report News & Analysis 12/4/2004 Post a comment The lack of new 65nm and 45nm tools will slow EDA revenue growth in 2004 and 2005, says research firm Gartner Dataquest in its new market trends report. The report also says the ESL market took a major hit, and that Synopsys lost market share in IC implementation and formal verification, but gained in signal integrity.
The why, where and what of low-power SoC design Design How-To 12/3/2004 Post a comment Minimizing power consumption is a huge challenge for nanometer systems-on-chip. In this tutorial article, Cadence Design Systems' Pete Bennett (right) shows why that's the case, and details techniques that can help, including multiple voltage domains, clock phasing, and clock gating.
SystemC drängt auf IEEE-Standardisierung Product News 12/2/2004 Post a comment Die Hardware-Beschreibungssprache SystemC hat den wichtigen Schritt vom einstigen Adhoc-Standard zum offiziellen IEEE-Entwurf geschafft. Anhänger von SystemC hoffen nun, dass sich die Sprache mit der künftigen IEEE-Absegnung bei EDA-Anbietern und Anwendern stärker durchsetzen wird.