Last minute deals open opportunities for 2007 and beyond Blog 12/31/2006 Post a comment In the week between Christmas and New Year, a semiconductor equipment company purchased an EDA company, and an EDA company increased its ESL expertise with the acquisition of a British company. And both events have given pundits cause for judgments, predictions, and the usual doomsday scenario. I thought the combined news exciting and full of promise.
Centralized storage caching fixes the EDA compute bottleneck Design How-To 12/31/2006 Post a comment EDA environments, with their demanding data intensive applications, often experience the pain of I/O bottlenecks. Scalable caching appliances deliver high capacity, high performance cache as a shared network service to accelerate data center performance. They connect to the network via standard Gigabit Ethernet, complementing existing storage to provide very high throughput and real time data access.
CoCreate's new PLM tool suite 'changes the rules' Product News 12/28/2006 Post a comment Innovation is the lifeblood of companies in the fast-moving electronics industry, yet the very process of product development can become a roadblock to beating a competitor to market. CoCreate Software Inc., a product lifecycle management software provider, is trying to eliminate those design bottlenecks using an approach to 3D product development the company calls "dynamic modeling."
Analyst Gary Smith: top 10 EDA topics for 2007 News & Analysis 12/28/2006 Post a comment Veteran EDA analyst Gary Smith explains his "top ten" list of hot EDA topics for 2007, including electronic system level (ESL), design for manufacturability (DFM), IP reuse, analog/RF, globalization, and multi-core systems on chip.
Formal provider OneSpin opens U.S. office News & Analysis 12/28/2006 Post a comment OneSpin Solutions, a formal verification spinoff from Infineon in Germany, has opened a U.S. office in Sunnyvale, Calif. to boost sales of its Module Verifier and Equivalence Checker products.
ESL pioneer Forte closes $5.4M funding News & Analysis 12/20/2006 Post a comment Aiming to expand its worldwide presence in behavioral synthesis, electronic system level (ESL) design provider Forte Design Systems has closed a series D round of venture funding for $5.4 million.
Cadence claims RTL synthesis boost Product News 12/19/2006 Post a comment A substantial R&D effort has boosted quality of silicon and slashed run times for Cadence Design Systems' RTL Compiler synthesis tool, said Pradeep Fernandes, vice president for synthesis R&D at Cadence.
DVCon 2007 sets technical program News & Analysis 12/18/2006 Post a comment The Design and Verification Conference (DVCon), set for Feb. 21-23, 2007 in San Jose, Calif., has announced a three-day technical program including tutorials, a keynote address, panel discussions, and paper presentations.
Practical Applications of Statistical Static Timing Analysis Design How-To 12/18/2006 Post a comment Statistical Static Timing Analysis (SSTA) becomes a necessity as a paradigm shift in timing analysis must be considered while the electronic design industry continues to push the limits of Moore's Law. The major reason for this is overly pessimistic timing analysis, which threatens to negate many of the benefits that smaller process geometries offer, when traditional static timing analysi is used.
PSL Verification Package for the Open Core Protocol Design How-To 12/14/2006 Post a comment A PSL Verification Package for the Open Core Protocol provides a flexible, powerful, and automatic verification method that complements the existing verification methodologies. The package improves both quality and efficiency of the functional verification by providing automation, simplifying debugging, and increasing visibility.
Wipro selects Cadence as primary tool provider News & Analysis 12/12/2006 Post a comment Cadence Design Systems is claiming a significant marketing success in India by tying its technology into the in-house design methodology devised by the world's largest independent R&D services provider, Wipro Technologies.
Startup weaves 'fabric' for IC design News & Analysis 12/12/2006 Post a comment Startup Fabbrix Inc., which is announcing a collaboration with PDF Solutions this week, aims to reshape IC design through the use of regular design patterns or "fabrics," says Larry Pileggi, CTO.
An outlook of EDA in 2007 News & Analysis 12/11/2006 Post a comment EDA vendors face a new challenge for 2007: support designers that target the latest process and require highly sophisticated tools and methods while also providing reliable and cheaper tools for those customers using less advanced techniques.
Overcoming high-volume IC design challenges to maximise profits Design How-To 12/11/2006 Post a comment The handcrafted blocks in high-volume ICs dictate the overall floorplan and limit the remainder to irregular topologies, while the layout of this circuitry forms the focus for key performance, area and design-rule improvements. A shape-based physical design platform offers the ability to design the entire net as a whole, taking into consideration design rules, timing, performance and area. Furthermore, the shape-based approach routes all of it at once, delivering results that are as good " if n
NEC's MCUs enhance memory, pin counts Product News 12/11/2006 Post a comment NEC Electronics America, Inc. has added sixteen new devices to its line of 16- and 32-bit all-flash microcontrollers. These MCUs offer up to twice the memory and a significant increase in pin-count options compared to previous devices in the line.
May you live an interesting week Blog 12/9/2006 Post a comment The week of December 4, 2006 was an interesting week in EDA. From product announcements that improve ESL utility to news about offshoring, to indications of the future of the DFM market and more.
In-circuit programmer supports Atmel AVR MCUs Product News 12/8/2006 Post a comment RPM Systems Corp. has launched its MPQ-AVR, a four-port, in-circuit programmer for Atmel AVR microcontrollers. The system features on-board flash storage of program images, and offers stand-alone, PC-controlled or ATE-controller programming modes.
Globalization in an Analog/Mixed-Signal World Design How-To 12/7/2006 Post a comment Today's companies must embrace the fact that the engineering world has changed. Demands for new and nimble engineering teams and work environments will continue. . Having a structure and protocol that enables international teams to work towards a common goal is something to establish—and, once in place, something to celebrate.
$8000 software is free to Agilent and Yokogawa realtime oscilloscope users Product News 12/4/2006 Post a comment Focusing on clock and timing engineering and related measurement science, Amherst Systems Associates announces a North American kickoff of a program that will aggressively give away premium oscilloscope analysis and productivity software. The company's M1 Oscilloscope Tools will go to targeted users of Agilent and Yokogawa realtime oscilloscopes.
PTO to reexamine Magma patent News & Analysis 12/4/2006 Post a comment The U.S. Patent and Trademark Office will reexamine one of two Magma Design Automation patents at issue in a high-profile lawsuit between Magma and Synopsys.
"Enterprise" System Level (ESL) Verification " PART II Design How-To 12/4/2006 Post a comment In the second of a two parts article, Ran Avinun discusses the need to address System Level Design at the Enterprise level recognizing the role that software and firmware play in modern SoC designs. The article suggests that EDA companies must develop support for software certification within ESL tools.
Layout tool speeds MEMS design Product News 12/1/2006 Post a comment GenISys has started sampling to designers of MEMS based devices, sensors and flat panel displays a flexible simulation platform for mask aligner lithography that lets them virtually model, redesign and optimize device layouts and processes in hours rather than weeks.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments