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Content tagged with Design Tools (EDA)
posted in December 2007
Verification Platform for Complex Designs
Design How-To  
12/31/2007   Post a comment
In this article the challenges faced in verifying today's complex designs are discussed. Along with, the corresponding advancements required in verification products and techniques to overcome these issues have been suggested.
Get research out of development
Blog  
12/26/2007   Post a comment
An engineer is a professional that uses available tools to develop the best possible solution to a problem. A scientist is a professional that explores new possibilities within a given field with the goal of creating new engineering tools.
The top-rated Planet Analog articles of 2007
Design How-To  
12/25/2007   Post a comment
See what the Planet Analog audience--your fellow designers--looked at the most in 2007
Understanding Clock Domain Crossing Issues
Design How-To  
12/24/2007   7 comments
In today's complex system on chip (SoC) designs, multiple clocks have become the norm. Thus, clock domain crossings (CDCs) are an integral part of any SoC. The main problems which can occur in a clock domain crossing are metastability, data loss and data incoherency. In this paper, we discuss all these issues for different types of synchronous and asynchronous clock domain crossings.
Efficient testbench implementation for verification proposed by Synopsys staffer
News & Analysis  
12/21/2007   Post a comment
A Synopsys India staffer has proposed an efficient implementation of testbench for verification of configurable host controller IP.
VME transceiver board delivers 10 dB performance boost
Product News  
12/21/2007   Post a comment
Pentek's Model 7141 provides two 125 MHz, 14-bit A/Ds and an FPGA and tools for custom DSP functions. The board's SNR and spurious free dynamic range are improved by 10 dB compared to the older Model 7140.
Dynamically-reconfigurable ECAs - Part 3 (Student Project #1)
Design How-To  
12/19/2007   Post a comment
In this case study, a PhD student at Virginia Tech (Abhranil Maiti) uses Element CXI's Elemental Computing Array (ECA) to implement a simple FIR filter.
Imperas to focus first on multiprocessor simulation, debug
News & Analysis  
12/18/2007   Post a comment
Imperas Ltd., a startup company developing multiprocessing development tools, has reorganized and refocused itself after a year of working with lead customers.
Free DSP cores!
Signal Processing DesignLine Blog  
12/17/2007   Post a comment
Structured ASIC company eASIC now offers Tensilica cores free of charge. If you have a medium-volume app, you should check this out.
A Strong Analog Statement
Blog  
12/17/2007   Post a comment
A close collaboration between EDA and analog foundries could improve design methods.
Actel presents battery-powered Icicle kit
Product News  
12/17/2007   Post a comment
Based on Actel's low-power IGLOO FPGAs, cool new Icicle board demonstrates extended battery life for portable designs.
Achieving Yield in the Nanometer Age
Design How-To  
12/17/2007   Post a comment
Designers and manufacturers are two sides of the same team, sharing a common goal " yield. To win out, they need to align their strategies, their skills and their knowledge, and work together to overcome the challenges. That's the way the game is played in the nanometer era.
Agilent Announces GoldenGate Plus
Product News  
12/15/2007   Post a comment
Agilent Technologies announced the availability of GoldenGate Plus for RFIC simulation, analysis and verification.
DVCon Announces 2008 Technical Program
News & Analysis  
12/14/2007   Post a comment
The Design and Verification Conference (DVCon) announced the 2008 technical program for the annual conference.
Researcher's methodology eases VLSI-layout updates
News & Analysis  
12/13/2007   Post a comment
A researcher has outlined a methodology that eases the process of recompiling large VLSI designs--a process that needs to be done from scratch after every update in traditional CAD.
MATLAB-to-C translation, part 3: Code generation and verification
Design How-To  
12/13/2007   Post a comment
Part 3 of this 3-part series examines the verification process and makes the case for automatic C generation.
New low-power FPGA-based video demo/development kit
Product News  
12/12/2007   1 comment
Attodyne's new demonstration-development board for Actel's low-power FPGAs controlling portable displays offers affordable and innovative IP deployment features.
Combination of Precision Synthesis and SmartGuide technology claimed to dramatically reduce design time
Design How-To  
12/12/2007   Post a comment
Dillon Engineering finds design cycle savings of 70% in recent tests of Precision Synthesis from Mentor combined with Xilinx SmartGuide technology.
Mouser Electronics stocks Cypress Semiconductor CY3209-ExpressEVK Evaluation Kit
Product News  
12/12/2007   Post a comment
CY3209-ExpressEVK Evaluation Kit, Capacitive Touch Interfaces, Programmable CY3209 kit offers numerous design examples with four separate programmable SoC (PSoC) mixed-signal arrays. Design, Mouser Electronics, Cypress Semiconductor, PSoC CapSense
ARC configures a design flow for system-on-chip
Design How-To  
12/12/2007   Post a comment
Configurable cores and subsystems developer ARC International (St. Albans, England) has developed and is refining a systems development platform that it says will change the way mobile multimedia systems are being designed.
Mentor adds MCMM to Olympus-SoC
Product News  
12/11/2007   Post a comment
Mentor has released its latest upgrade of the Olympus-SoC product with significant SI and MCMM capabilities.
Tensilica enhances Xtensa cores and tools
Product News  
12/11/2007   Post a comment
Tensilica has shrunken the minimum core size of its Xtensa 7 and Xtensa LX2 configurable processor families. It has also enhanced the Xtensa Xplorer design environment to make customization easier and faster.
Danger: High Competition. Use Extreme Caution
Blog  
12/11/2007   Post a comment
Integration of DFM functions into place and route tools will disrupt the size and dynamics of the DFM market segment.
MATLAB to C showdown
Signal Processing DesignLine Blog  
12/11/2007   Post a comment
Catalytic MCS and Embedded MATLAB both generate C from MATLAB, but there are big differences between the products. Here's the scoop.
New equivalence checker dedicated to FPGA synthesis verification
Product News  
12/10/2007   Post a comment
OneSpin Solutions delivers the 360 EC-FPGA equivalence checker, which is claimed to be the first such tool dedicated to FPGA synthesis verification.
ATopTech Releases Aprisa
Product News  
12/10/2007   Post a comment
Aprisa is a netlist-to-GDSII physical design solution that includes floorplanning, placement, clock tree synthesis (CTS), global routing, and detailed routing.
ATopTech, a New Face in Physical Design
News & Analysis  
12/10/2007   Post a comment
ATopTech announced its existence, introduced first product, and disclosed business deal with Broadcom.
Applying Constrained-Random Verification to Microprocessors
Design How-To  
12/10/2007   Post a comment
This article proposes an object-oriented solution for processor verification. The solution covers both a top-down stimulus planning process and a bottom-up implementation solution using SystemVerilog and commercially available base classes.
Cyclone III FPGA-based kit used in video design and evaluation kit
Product News  
12/7/2007   Post a comment
The Microtronix ViClaro III kit, with Altera's Cyclone III FPGA as its engine, provides a comprehensive engineering design and evaluation platform.
Virtually every ASIC ends up an FPGA
Design How-To  
12/7/2007   Post a comment
Because more than 90 percent of all ASICs today are either partially or completely prototyped in FPGAs before tape-out, the question is no longer whether to implement an IC design as an ASIC, or as an FPGA. To meet the demands of today's markets, most design teams must do both.
New tool suite for programming massively parallel processors
Product News  
12/6/2007   Post a comment
Ambric's aDesigner software development tool suite for programming massively parallel processors offers ease-of-use, scalability, and a deterministic programming model.
A revolution in functional verification
Design How-To  
12/6/2007   1 comment
Exhaustive functional coverage promises to revolutionize the design of ICs and other digital systems.
Catalytic Announces Function Library
Product News  
12/5/2007   Post a comment
Catalytic Inc has announced immediate availability of Catalytic Function Library, a significant addition to its MCS (MATLAB to C Synthesis).
Dynamically-reconfigurable Elemental Computing Arrays (ECAs) - Part 2 (Programming Model)
Design How-To  
12/5/2007   2 comments
ASICs, FPGAs, CPUs/DSPs, and SoCs have been joined by a new kid on the block - the Elemental Computing Array (ECA) from Element CXI.
OSCI issues new TLM standard
News & Analysis  
12/5/2007   Post a comment
The Open SystemC Initiative is circulating a proposed standard TLM-2 for review.
Xilinx delivers Virtex-5 FPGA-based solutions for SPI-4.2 and SFI-4.1 interfaces
Product News  
12/4/2007   Post a comment
High-performance Virtex-5 FPGA-based hardware verification board and IP from Xilinx enables quick implementation of OC192 (10 Gbps) wired networks.
EDA standards organization gets an award
Blog  
12/4/2007   Post a comment
The DASC was awarded the Sponsor Award for Outstanding Contribution to Corporate Standards Development by the IEEE-SA.
Green Hills tailors toolkit for 405EZ embedded processor
Product News  
12/4/2007   Post a comment
Green Hills has developed a software development toolkit targeting Applied Micro Circuit Corp.'s Power Architecture 405EZ embedded processor, a 32-bit RISC device.
MCU self-test software simplifies product safety compliance
Product News  
12/4/2007   Post a comment
This self-test software for the STM32 MCU from STMicroelectronics is designed to simplify the testing and securing end-product approval and compliance with the demands of the IEC 60335-1 standard, when the MCU is used in household appliances.
Using DFM Routing to Impact Design Performance and Yield
Design How-To  
12/4/2007   Post a comment
As design teams continue to drive forward with the use of advanced process technologies there has been much discussion about the use of design-for-manufacturing (DFM) techniques and questions about the real usefulness and effectiveness of DFM. This paper describes an experiment conducted to establish the quantitative performance and yield impact of proactively using DFM techniques during the routing of a design.
Free trial version of Eridon's UnifiedLogic for Xilinx Spartan-3 kits
Product News  
12/3/2007   Post a comment
UnifiedLogic automatically customizes and configures the RTOS and drivers and integrates peripherals around an FPGA for both prototype and production hardware.
Cadence Boosts Enterprise Verification Offering
Product News  
12/3/2007   Post a comment
New Aspect-Oriented Generation Engine and Advanced Transaction-Based Acceleration; Supports Open Verification Methodology for SystemVerilog
Leveraging system models for RTL functional verification
Design How-To  
12/3/2007   Post a comment
Register transfer level (RTL) verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70 percent of the total design effort.
MATLAB-to-C tool get major upgrade
Product News  
12/3/2007   Post a comment
Catalytic's MATLAB-to-C tool can now generate C code for over 300 MATLAB functions, including functions from the signal processing, communications, imaging, and math toolboxes.


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Rishabh N. Mahajani, High School Senior and Future Engineer

Future Engineers: Don’t 'Trip Up' on Your College Road Trip
Rishabh N. Mahajani, High School Senior and Future Engineer
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A future engineer shares his impressions of a recent tour of top schools and offers advice on making the most of the time-honored tradition of the college road trip.

Max Maxfield

Juggling a Cornucopia of Projects
Max Maxfield
2 comments
I feel like I'm juggling a lot of hobby projects at the moment. The problem is that I can't juggle. Actually, that's not strictly true -- I can juggle ten fine china dinner plates, but ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
28 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Karen Field

July Cartoon Caption Contest: Let's Talk Some Trash
Karen Field
127 comments
Steve Jobs allegedly got his start by dumpster diving with the Computer Club at Homestead High in the early 1970s.

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