Virage Logic cuts quarterly guidance News & Analysis 12/30/2008 Post a comment Citing the increasing effect of the global financial crisis, IP vendor Virage Logic lowered revenue and earnings guidance for the company's fiscal first quarter, which ends Dec. 31.
Report calls for restructuring patent office News & Analysis 12/19/2008 Post a comment The U.S. Patent and Trademark Office needs to be overhauled if it is to come to grips with rising backlogs and a perception of declining patent quality, according to a report the U.S. Chamber of Commerce sent to President-elect Barack Obama.
ST, Synopsys partner to deliver complete design flow for 32-nm News & Analysis 12/18/2008 Post a comment Synopsys, Inc. (Mountain View, Calif.) and STMicroelectronics NV (Geneva, Switzerland) have joined efforts to enable the readiness of key components in a 32-nm design flow, including ST's standard cell library for low power and high-performance design, and the support of the latest route rules in Synopsys' IC Compiler Zroute technology.
Analysis: Did Cadence hit rock bottom? News & Analysis 12/17/2008 Post a comment EDA vendor Cadence Design System hasn't had much to cheer about lately. But the company's stock enjoyed a relative surge after an analyst upgrade, prompting the question of whether the company hit rock bottom and is in rebound mode.
Video: NASA wants you in space Product News 12/17/2008 Post a comment Four companies and a team from MIT Space Systems Laboratory announced their intention to compete for the Google Lunar X Prize, one of many efforts NASA hopes to inspire as part of its drive to promote more commercial exploration and use of space, often using off-the-shelf technologies.
Process variability still vexing designers News & Analysis 12/17/2008 Post a comment CMOS device process variability remains one of the most acute problems facing the semiconductor industry, particularly at the 45-nm node and beyond, according to presenters at the International Electron Devices Meeting.
Planning, adopting and implementing adaptive reuse Design How-To 12/16/2008 Post a comment Reuse of IP in a different context, which would turn one perfectly functioning chip into an inoperable one, has caused many to be cautious when it comes to whole-heartedly embracing reuse. Streamlining, breaking the problem into manageable pieces and reducing degrees of interaction complexities are benefits ofreuse intent and practice.
Cadence Q3 revenue falls 42% News & Analysis 12/10/2008 Post a comment Embattled EDA vendor Cadence Design Systems reported third quarter revenue of $232 million, a decrease of 42 percent from the same period of 2007. The company also announced it would revise its first and second quarter results downward by a total of nearly $38 million as the result of a previously announced investigation into improper revenue recognition.
EDA tools for FPGAs running out of gas News & Analysis 12/10/2008 1 comment The field-programmable gate array (FPGA) market has experienced lackluster and flat growth in recent times. But now, the sector faces a set of new challenges that could threaten the business.
Security alert: Beware of USB memory sticks News & Analysis 12/9/2008 1 comment The next time you find a USB memory stick in a parking lot or outside your house, think twice before plugging it in: It could cost you your intellectual property or personal identity. That was the startling alert put out by Adriel Desautels, chief technology officer at anti-hacking specialist firm NetraGard. And it's only the start.
EDA Rescue Plan Programmable Logic DesignLine Blog 12/9/2008 Post a comment I just received an email from a company called Blue Pearl Software that, if nothing else, managed to grab my attention.