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Content tagged with Design Tools (EDA)
posted in February 2002
Einstein Ratio for Electrons in Silicon under a High Electric Field
Design How-To  
2/27/2002   Post a comment
Shrinking process technologies have brought many semiconductor-material effects that affect device performance and reliability to the forefront. Vijay K. Arora of Wilkes University in Pennsylvania discusses the variation of the Einstein ratio between carrier diffusion coefficient and mobility under a high electric field, which impacts submicron-device characterization.
Chartered now offers free access to Avanti and Artisan design libraries
News & Analysis  
2/25/2002   Post a comment
SINGAPORE -- Chartered Semiconductor Manufacturing Pte Ltd. here today announced it is offering foundry customers free access to Avanti Corp.'s Libra-Visa design libraries for development and analysis of products prior to production.
Atrenta focus on distribution
News & Analysis  
2/24/2002   Post a comment
Atrenta, the design tools company spun off from Interra, is looking for a European distributor for the latest release of its predictive analy-sis Spyglass software.
Memory tool aims for Spice accuracy on full-chip simulations
News & Analysis  
2/21/2002   Post a comment
US design tools specialist Circuit Semantics has developed a characterisation and modelling tool for embedded static memories that generates full-chip timing models with an accuracy close to that of Spice.
Agilent, Cadence pool technologies for RF/mixed-signal IC development
News & Analysis  
2/14/2002   Post a comment
PALO ALTO, Calif.-- Agilent Technologies Inc. and Cadence Design Systems Inc. today announced a "far-reaching" alliance to combine their technologies to accelerate development and testing of next-generation ICs for wireless and wireline communications systems.
Service groups start to turn internal tools into products
News & Analysis  
2/13/2002   Post a comment
Design automation tools companies are beginning to use their design services arms as testbeds for their tools and, in some cases, to provide new tools where they have built up expertise in areas missed by the commercial players.
SystemC rollout to design groups under way at ST
News & Analysis  
2/13/2002   Post a comment
STMicroelectronics has started to roll out tools based around the SystemC language to its design groups as it begins the process to standardise systems modeling techniques across the company on a language the company helped drive initially. The first few design groups are now using the language and a toolset built by ST and Synopsys.
ChipWrights lines up tools, kernel for new DSP-based processor
News & Analysis  
2/11/2002   Post a comment
NEWTON, Mass. -- Fabless semiconductor startup ChipWrights Inc. here today announced it has licensed compiler and debugger technology from Metrowerks, a development tool supplier owned by Motorola Inc., for use with its new DSP-based processor.
Design team says RISC processor is first diagonally interconnected IC
News & Analysis  
2/6/2002   Post a comment
SAN FRANCISCO -- A 200-MHz RISC processor has become the first IC to be successfully laid out with diagonal interconnect lines as proposed under the "X Architecture" initiative, said a technical paper presented by Toshiba Corp., its ArTile subsidiary and Simplex Solutions Inc. at the International Solid-State Circuits Conference (ISSCC).
Defining platform-based design
News & Analysis  
2/5/2002   Post a comment
Ultrasparc III Passes Physical Verification
News & Analysis  
2/1/2002   Post a comment
Since 1990, Sun Microsystems has tracked factors affecting design complexity and productivity with an extensive set of indicators.
Digital Video IC Set For Debugging Ride
Design How-To  
2/1/2002   Post a comment
With the decreasing feature sizes of state-of-the-art process technologies, design teams are faced with the challenge of quickly and efficiently mapping high-level functions onto a growing number of available transistors.
Subwavelength Size Traces Design Flows
Design How-To  
2/1/2002   Post a comment
As the semiconductor industry hit the 0.18-micron generation, it entered a new regime. For the first time, leading-edge device feature sizes became significantly smaller than the wavelength of light used by available best-in-class optical-lithography equipment.
Optimum Design via 'Smart' Partitioning
Design How-To  
2/1/2002   Post a comment
Communications systems continue to grow increasingly complex as product-development times shrink.
Smart Partitioning could be path to Integration
Design How-To  
2/1/2002   Post a comment
As systems-on-chip become more pervasive, designers will need to address the question of when to integrate RF functionality on more and more projects.
MCM and BGAs Characterization using Planar EM Simulation
Design How-To  
2/1/2002   Post a comment
When designing at multi-GHz frequencies, you need to include accurate IC-package models and analysis. Agilent's Jim DeLap reviews MCM and BGA technologies, simulation issues, and EM simulator requirements, along with several practical simulation examples.


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