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Content tagged with Design Tools (EDA)
posted in February 2003
Transaction-based methodology supports HW/SW co-verification
News & Analysis  
2/28/2003   Post a comment
Using an ARM-based SoC as an example, Axis Systems' Jason Andrews offers a detailed walkthrough of the hardware/software co-verification process, and introduces a new transaction-based debugging approach.
Vendors debate viable IP business model
News & Analysis  
2/24/2003   Post a comment
Three IP vendors debated the question of how to make silicon intellectual property into a viable business, during a panel discussion here moderated by E.E Times editor-in-chief Brian Fuller.
Artisan completes Nurlogic acquisition
News & Analysis  
2/21/2003   Post a comment
Artisan Components, Inc. (Sunnyvale, Calif.) announced the completion of its acquisition of NurLogic Design Inc. (San Diego), a provider of analog intellecutal property (IP) and high-bandwidth connectivity cores.
The case for logic BIST
News & Analysis  
2/14/2003   Post a comment
Researchers scale power barrier at ISSCC
News & Analysis  
2/10/2003   Post a comment
Marking its 50th anniversary, the 2003 International Solid State Circuits Conference (ISSCC) in San Francisco has chosen a fitting theme: "Power-aware systems".
Moving to the GHz plus range in SoC design?
Design How-To  
2/10/2003   Post a comment
Design methodologies allow us to build anything fast, from gigahertz microprocessors to multigigahertz RF cores.
Keeping leakage current under control
Design How-To  
2/10/2003   Post a comment
As process technologies progress from 0.18 microns to 130 nanometers, it is no longer sufficient to achieve closure on timing, IR drop, and signal integrity.
Integration for Performance
News & Analysis  
2/10/2003   Post a comment
Integration by function puts more features, interfaces into handsets
Design How-To  
2/10/2003   Post a comment
The large number of complex air interfaces and wafer process technologies along with advanced applications processing make the integration of advanced wireless handsets a considerable challenge.
Global strategy needed for integrating IP in complex SoC design
News & Analysis  
2/10/2003   Post a comment
The unspoken domino theory of chip design is starting to break down in a big way with many current SoC projects.
Burning rubber on the SoC freeway
News & Analysis  
2/10/2003   Post a comment
Trading off performance for power has never been an easy task. This week we'll take a look at how some developers are managing to juggle the gigahertz-performance requirements of today's huge system-on-chip designs and the demands those systems make on power consumption.
Adding net functions to GHz chips
News & Analysis  
2/10/2003   Post a comment
With the push to smaller geometries, chip functionality continues to increase. Clock frequencies of 100 MHz at 0.18- and 0.13-micron manufacturing technologies are quite common.
Reaching for the 1 GHz ring
Design How-To  
2/10/2003   Post a comment
Gigahertz design is a very exclusive neighborhood that requires skilled hand-crafting by teams of engineers during all phases of a design.


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