Free simulation software gets supply designers ON board Product News 2/28/2004 Post a comment ON Semiconductor's ON Power Designer, a complimentary, customized version of Power 4-5-6 Plus from Ridley Engineering, Inc. (Roswell, GA), is suited to development of both active and standby power supplies for computing, LCD monitors, battery chargers, and wall adapters working from an 85 to 260V input. The NCP120x software product, for switching supplies, provides circuit design synthesis, large-signal waveform simulation and control-loop design, plus a magnetics designer and final parts list.
EDA CEOs predict growth, cite cost concerns News & Analysis 2/28/2004 Post a comment As the semiconductor business continues a slow recovery, the cost of keeping up with Moore's Law is a foremost issue on the minds of EDA customers, said EDA CEOs attending Thursday night's (Feb. 26) EDA Consortium forecast panel.
FPGA, PCB tools must work together News & Analysis 2/27/2004 Post a comment PCB designers need signal integrity models for FPGAs, and they may need to change pin-out assignments. What's needed is tight integration of FPGA tools and PCB design tools, says Mentor Graphics' John Isaac.
Training firm offers free verification IP News & Analysis 2/27/2004 Post a comment As a way of spreading the word about its classes and workshops, Si-Concepts is offering a free Vera TCP/IP packet generator with a built-in functional coverage tracker. The company is also offering a tutorial on coverage-driven testbenches at the DVCon conference March 1, 2004.
SystemVerilog enhancements for all chip designers News & Analysis 2/26/2004 Post a comment SystemVerilog isn't only for engineers doing system-level design; it provides extensions to Verilog that are useful for anyone doing chip design. In this tutorial, consultant Stu Sutherland (right) describes 14 enhancements that will be helpful to all Verilog users.
Starc to release Starcad-21 design methodology News & Analysis 2/25/2004 Post a comment Using the know-how of its 10 semiconductor member companies, the Semiconductor Technology Academic Research Center (Starc) will release version 1 of a chip design methodology named StarCAD-21 this month that covers silicon implementation from RTL to GDSII.
Analog EDA startup preps optimization tools News & Analysis 2/25/2004 Post a comment Claiming new technology from the Catholic University of Leuven, Belgium, startup Kimotion Technologies is preparing products that provide modeling, sizing and layout for analog and mixed-signal IC designs. The company will offer the "next generation" of analog EDA, said Oscar Buset, CEO (right).
Magma buys IC verification startup Mojave News & Analysis 2/24/2004 Post a comment Moving aggressively into the design for manufacturability (DFM) market, Magma Design Automation announced Tuesday (Feb. 24) that it will acquire Mojave Design, a much-awaited startup launched by former Avanti Corp. executives. Magma will use Mojave's technology to bring DFM analysis into its RTL-to-GDSII implementation flow.
QuickSilver's silicon-to-go News & Analysis 2/24/2004 Post a comment This detailed look at QuickSilver's adaptive computing machine (ACM) technology shows how you can bring algorithms into silicon, using a toolset and IP available under a modified open-source license.
Looking for excitement in PCB CAD News & Analysis 2/23/2004 Post a comment PCB layout appears to have become a sleepy backwater of the EDA industry. But there is some sizzle in the PCB design market, if you look beyond layout to signal-integrity and thermal analysis tools, virtual prototyping, and packaging.
Using S parameters for signal integrity analysis News & Analysis 2/23/2004 Post a comment S parameters aren't just for microwave engineers any more; they're becoming important for analog and digital design. In this feature, Optimal's Ching-Chao Huang (right) reveals methods that will help you get accurate S parameters for signal integrity analysis.
Language adoption will drive IC design News & Analysis 2/23/2004 Post a comment Why wait for standardization? SoC design success provides the best practical push to speed language adoption and certification, says Frank Weiler, general chair of next week's Design and Verification Conference (DVCon).
IBM, Tera claim RTL handoff flow News & Analysis 2/23/2004 Post a comment Stepping toward a new paradigm in chip design, Tera Systems Inc. and IBM Microelectronics this week will begin offering what they call the first production-ready RTL handoff flow. It allows designers to skip synthesis and IC implementation.
CoWare unveils processor design suite News & Analysis 2/17/2004 Post a comment CoWare Inc. will unveil the latest version of its LisaTek embedded-processor design tool suite at the Design Automation and Test in Europe (DATE) conference in Paris this week. Version 2004.1 adds C compiler and RTL-generation technologies to the suite.
Cadence rolls synthesis tool, new metric News & Analysis 2/17/2004 Post a comment Cadence Design Systems Inc. this week will announce that its Encounter RTL Compiler Ultra synthesis tool supports the VHDL language. The company is also proposing a new quality-of-silicon (QoS) metric to evaluate synthesis results.
EDAC road map to track supplier OS support News & Analysis 2/16/2004 Post a comment The EDA Consortium is publishing a road map on its Web site this week that recommends timelines by when vendors are to support various operating systems. The map will help guide EDA vendors and help customers determine when tools will be available.
Synopsys, ARM to write SystemVerilog manual News & Analysis 2/16/2004 Post a comment Seeking to write the book on how to use SystemVerilog for verification, Synopsys Inc. and ARM Ltd. are working together on a SystemVerilog Verification Methodology Manual and hope to have it ready by June.
Ansoft jumps into RF IC modeling News & Analysis 2/16/2004 Post a comment Ansoft Corp. will introduce a circuit simulator this week designed to compete with HSpice and SpectraRF in time-domain analysis of high-frequency circuits, and with Agilent EEsof tools in frequency-domain analysis. Ansoft's Nexxim serves as both a circuit simulator for time-domain analysis and as a harmonic balance simulator for the frequency domain, the company said.
'Quality of Silicon' metric gauges EDA tool success News & Analysis 2/12/2004 Post a comment The "Quality of Results" (QoR) metric created to evaluate synthesis tools no longer works in the nanometer era, says Cadence Design Systems' Steve Carlson (right). In this feature, he shows how to derive a "Quality of Silicon" (QoS) metric for speed, area, and power that can be applied to all RTL-to-GDSII tools.
DVCon finalizes program, adds Bingham keynote News & Analysis 2/12/2004 Post a comment The 2004 Design and Verification Conference (DVCon) has announced its final program, including a keynote speech by Ray Bingham, Cadence Design Systems CEO. DVCon will be held in San Jose, California March 1-3, 2004.
Neolinear adds new features to synthesis tool News & Analysis 2/11/2004 Post a comment Neolinear Inc. has added such features as Monte Carlo analysis for predicting and improving the yield of a given design in version 3.0 of its NeoCircuit analog sizing and synthesis tool. Circuit sizing has been around for a few years now," said Graham Etchells, vice president of marketing for Neolinear. "The trick is not just finding a design point that works, but finding one that works and yields well." Mike Santarini has the story.
Addressing packaging concerns of low-k silicon News & Analysis 2/11/2004 Post a comment Ultrafine feature sizes and high performance requirements have necessitated the integration of low-k dielectrics on silicon-level interconnects that are mechanically weaker than previous-generation materials, a fact that has been recognized to be an industrywide issue.
Designing analog circuits in CMOS News & Analysis 2/11/2004 Post a comment The evolution in CMOS technology dictated by Moore's Law is clearly beneficial for designers of digital circuits, but it presents difficult challenges, such as lowered nominal supply voltages, for their peers in the analog world who want to keep pace with this rapid progression.
Designers wary as IBM embraces statistical timing News & Analysis 2/9/2004 Post a comment As IBM Corp. champions statistical timing to stem the rising tide of variations in deep-submicron CMOS processes, a debate is raging over whether probabilistic approaches should indeed supplant deterministic timing methods, said participants at last week's Tau Workshop on digital timing.
Cadence vows to bridge design database divide News & Analysis 2/9/2004 Post a comment In a step forward for EDA tool interoperability, Cadence Design Systems Inc. is building a "bridge" between Synopsys Inc.'s widely used Milkyway database and the fledgling industry-standard OpenAccess database.
Design flow integration comes to EDA world News & Analysis 2/6/2004 Post a comment Design flow integration is essential for sub-wavelength ICs, and difficult. But the OpenAccess Coalition is showing that it can be done, says Steve Schulz, Silicon Integration Initiative president.
Reshaping the SoC power design flow News & Analysis 2/6/2004 Post a comment Existing static sign-off flows fail to catch power problems in complex SoCs, according to Apache Design Solutions CEO Andrew Yang (right) and CTO Shen Lin. In this exclusive feature, they outline a new physical power flow that is based on power prototyping and full-chip dynamic power signoff verification.
EDA licensing needs overhaul, speakers say News & Analysis 2/5/2004 Post a comment The EDA industry needs licensing models more closely tied to customers' value propositions, according to panelists at a DesignCon conference executive forum here Wednesday. Missing from the discussion, however, were the big EDA vendors, whose "all you can eat" licensing policies came under repeated fire.
IBM uses "EinsStat" statistical analysis timing tool News & Analysis 2/3/2004 Post a comment As performance gains become harder to wring out of CMOS scaling, the chip industry increasingly will need to create more powerful design techniques to keep the chip industry on a growth path, said IBM fellow Jim Kahle during a keynote speech at the 2004 Tau Workshop Monday (Feb. 2nd).
Startup's tool set spans logical, physical design News & Analysis 2/2/2004 Post a comment A tool from startup Silicon Dimensions Inc. helps logic engineers approach design closure on block-level designs, says Don Zereski (right), president. The Chip2Nite tool provides floor planning, placement, analysis and optimization.