Design Con 2015
Breaking News
Content tagged with Design Tools (EDA)
posted in February 2005
Page 1 / 2   >   >>
Unified methodology enables full-chip test
News & Analysis  
2/28/2005   Post a comment
Disconnected point tools don't provide a good design for test strategy. Cadence Design Systems' Mick Tegethoff (right) describes a "unified" full-chip approach that spans test specification, implementation, and verification.
Le PDG de Cadence déclare que le marketing de la CAO doit changer
News & Analysis  
2/28/2005   Post a comment
A l’occasion d’une visite dans les centres indiens de Cadence situés à Noida, près de New Delhi, et à Bangalore, le Président-directeur général de Cadence, Michael J. Fister a déclaré que les entreprises de CAO allaient davantage prendre conscience des besoins du client et qu’elles n’allaient plus seulement représenter un secteur qui se permet des tentatives d’intimidation par des babillages technologiques.
Les PDG du secteur de la CAO affichent un optimisme modéré pour 2005
News & Analysis  
2/28/2005   Post a comment
Personne ne prévoit une croissance à deux chiffres du secteur de la CAO électronique, mais, en 2005, des recettes modestes devraient être enregistrées. Lors du Consortium sur la CAO, six PDG ont évoqué les nouveaux défis et les opportunités du secteur de la CAO.
32-bit ARM9 based SoCs now available with OSE 5.0 operating system
Product News  
2/26/2005   Post a comment
Enea Embedded Technology is porting Version 5.0 of the OSE Real-Time Operating System to the LH7A400 ARM-based BlueStreak SoC to improve the performance of mobile terminal devices
Cadence CEO says EDA marketing must change
News & Analysis  
2/25/2005   Post a comment
EDA companies will be more cognizant of customer needs and rise above being an industry that is one indulging in technology babble, Cadence president and chief executive Michael J. Fister said in a visit to Cadence's India centers at Noida near New Delhi and Bangalore.
Verifizierung - die Feuerprobe für die IP-Wiederverwendung
News & Analysis  
2/25/2005   Post a comment
Die Wiederverwendung von Intellectual Property (IP) gilt in der Chipbranche als Allheilmittel für komplexe Schnittstellen und knappe Time-to-Market-Vorgaben. Dabei darf nicht vergessen werden: Auch die Wiederverwendung von IP ist mit Kosten verbunden, und auf der Weg zum Erfolgschip lauern etliche Fallstricke.
EDA CEOs moderately bullish for 2005
News & Analysis  
2/25/2005   Post a comment
No one is predicting double-digit growth for the EDA industry, but 2005 should bring some modest gains, according to participants in the annual CEO forecast panel at an EDA Consortium meeting here Thursday night (Feb. 24).
Acoustic echo cancellation and noise suppression libraries
Product News  
2/25/2005   Post a comment
Software libraries provide a cost-effective, easy way to improve sound quality and intelligibility
RTL synthesis support is downloadable
Product News  
2/25/2005   Post a comment
Precision synthesis supports all lattice digital devices including latticeECP-DSP and latticeEC FPGAs
Breaking the Verification Barriers
Design How-To  
2/24/2005   Post a comment
Verification automation and re-use of qualified verification components is a must for safety in electronic systems.
M. d’Eyssautier quitte ses fonctions de directeur général de Cadence Europe
News & Analysis  
2/24/2005   Post a comment
Guillaume d’Eyssautier, vice-président et directeur général pour l'Europe de Cadence Design Systems Inc. (San Jose, Californie), va quitter ses fonctions, selon une source proche de la société.
Agere ouvre un nouveau centre de conception en Inde
News & Analysis  
2/24/2005   Post a comment
Dans le cadre de son expansion, Agere Systems ouvre un deuxième site de développement en Inde. Celui-ci vient s’ajouter à un site existant créé en 1998 lorsque la société faisait partie du groupe Lucent Microelectronics.
Integrated design environment gives optimizing support for Flash-based FPGA families
Product News  
2/24/2005   Post a comment
Software allows customers to fully leverage all architectural features and performance of the new low-cost devices and enables device serialization
200-MHz prototyping platform targets multimedia
News & Analysis  
2/23/2005   Post a comment
Targeting a broad range of multimedia applications, ProDesign USA has announced ChipIt Gold Edition Pro, an FPGA-based verification platform for ASIC and system-on-chip designs. It claims to run at over 200 MHz, potentially allowing real-time operation.
Implement digital filters with LabVIEW
Product News  
2/23/2005   Post a comment
Are you a National Instruments LabVIEW user? If so, you'll be interested in NI's new LabVIEW Digital Filter Design Toolkit Version 7.5. The kit includes tools for modeling and creating software-based digital filters, as well as FPGA and C code generation for chip-level implementation.
Agere adds India design center
News & Analysis  
2/22/2005   Post a comment
Agere Systems has opened a second development site here as part of its expansion, joining an existing site set up in 1998 when the company was part of the Lucent microelectronics group.
Ultra-Wide-Band (UWB) and Serial Attached SCSI (SAS) verification components now available
Product News  
2/22/2005   Post a comment
IP portfolio touts expanded offering and extended modular reusability to UWB and SAS
Indicators help manage coverage-driven verification
Design How-To  
2/21/2005   Post a comment
Services firm Ace Verification uses global and local indicator charts to implement and track functional coverage. Akiva Michelson (right), Ace CTO, shows how and why, and describes how verification management tools can help.
Need for debug doesn't stop at first silicon
Design How-To  
2/21/2005   Post a comment
Today's silicon debugging is based on ad-hoc methods. A new generation of tools is needed for post-silicon debug, says Novas CEO Scott Sandler.
Got system-level synthesis?
News & Analysis  
2/18/2005   Post a comment
Is true high-level synthesis here at last? It's been a long hard road, but a look inside Forte Design Systems' Cynthesizer suggests it may be.
Cadence will EDA-Abrechnungsmodell ändern
Product News  
2/18/2005   Post a comment
Cadence Design Systems überlegt fieberhaft, wie man Kunden geschickter zur Kasse bitten kann. Laut Mike Fister, President und CEO von Cadence, sucht der EDA-Tool-Anbieter nach Alternativen zum üblichen Lizenzmodell. Ein Schritt, den der EDA-Riese elegant als "Evolution des Geschäftsmodells" umschreibt.
Les ventes de Synopsys baissent de 15% au 1er trimestre 2005
News & Analysis  
2/17/2005   Post a comment
Le géant californien de la CAO électronique, Synopsys Inc. a publié un chiffre d’affaires de 241,3 millions de dollars au titre de son premier trimestre fiscal, soit une baisse de 15% par rapport au chiffre d’affaires de 285,3 millions de dollars pour la même période de l’année dernière.
Sequence launches Indian tool development effort
News & Analysis  
2/17/2005   Post a comment
Sequence Design Inc., has launched a "Made in India" program aimed at fueling EDA tool development in India.
Un Français nommé directeur marketing de la division Emulation de Mentor Graphics
News & Analysis  
2/17/2005   Post a comment
Mentor Graphics, fournisseur de solutions de conception électronique pour le matériel et le logiciel, annonce la nomination de Jean-Luc Droitcourt en tant que directeur marketing de la division Emulation. Il rapportera directement à Eric Selosse, vice-président et directeur général de la division Emulation au niveau mondial.
Synopsys loss meets guidance as license revenue falls
News & Analysis  
2/17/2005   Post a comment
EDA vendor Synopsys Inc. posted a GAAP loss of $14.6 million, or 10 cents per share, on sales of $241.3 million in its first 2005 fiscal quarter ended Jan. 31, ostensibly due to the company's shift from an upfront to time-based license revenue model.
Synopsys posts loss in quarter, sales dips 15%
News & Analysis  
2/17/2005   Post a comment
EDA giant Synopsys Inc. reported revenue of $241.3 million in its first fiscal quarter, a 15 percent decrease compared to revenue of $285.3 million for the first quarter of fiscal 2004.
Benchmarks Identify Best Power Train Microcontrollers
Design How-To  
2/16/2005   Post a comment
A benchmark that has been designed specifically for automotive power train applications best represents how a particular device performs in that environment.
Synopsys expands lawsuit against Magma
News & Analysis  
2/16/2005   Post a comment
A bitter legal fight between Synopsys Inc. and Magma Design Automation intensified this week (Feb. 14) as Synopsys filed an amended complaint that adds charges of fraud and conversion to the previous allegations of patent infringement. It's just legal posturing to create a news event, according to Magma.
Sequence closes second round of funding
News & Analysis  
2/16/2005   Post a comment
EDA firm Sequence Design Inc. said it is about to close a second round of venture funding of $6 million, which the company said is enough to set it on the path to profitability
Chip-Ausbeute wird heißes Thema für Designer
News & Analysis  
2/16/2005   Post a comment
Mit zwei neuen Libraries schlägt die Chipbranche bei 'Design-for-Yield'-Lösungen (DFY) einen neuen Kurs ein. Die eine Routinensammlung stammt von einer Foundry, die andere von einem unabhängigen Anbieter. Damit wird die Chipausbeute zunehmend etwas, um das sich die Chipdesigner Gedanken machen müssen.
EDA 'bigwigs' field provocative questions
News & Analysis  
2/16/2005   Post a comment
EDA executives sparred over a variety of topics at the Design and Verification Conference (DVCon) "Bigwigs Panel" moderated by industry gadfly John Cooley Tuesday (Feb. 15).
See Solutions to 2005's Technology Challenges at DAC
Design How-To  
2/16/2005   Post a comment
In this feature article, William Joyner, Jr., General Chair of the 42nd Design Automation Conference, shares his predictions for EDA in 2005. Among the topics covered are electronic system level (ESL) design, power and signal integrity, design for manufacturing (DFM), and design verification.
Rhines draws roadmap for verification
News & Analysis  
2/16/2005   Post a comment
Mentor Graphics Chairman and CEO Walden Rhines provided the DVCon conference with roadmap for achieving progress in the battle for design verification productivity.
Lowest cost FPGA gets complete hardware support
Product News  
2/15/2005   Post a comment
Development solutions enable ISP and security features of Flash-Based FPGAs
Economical FPGA's benefit from new downloadable design tool
Product News  
2/15/2005   Post a comment
Advanced logic design tools now available via download, supports larger and less expensive FPGAs with embedded functional blocks.
Industry's only 4-state hardware - assisted verification solution?
Product News  
2/15/2005   Post a comment
Accurate hardware accelerator for functional verification propogates unknowns and tristate levels
Coverage is the heart of verification
News & Analysis  
2/14/2005   Post a comment
Coverage-driven verification is essential for large design projects, says Synopsys' Thomas Anderson. In this tutorial, he explains code, functional, and assertion coverage, along with other kinds of coverage metrics.
Lattice Semi in-system configuration engine goes into JTAG system
Product News  
2/14/2005   Post a comment
JTAG vendor ASSET InterTech is integrating into its existing ScanWorks boundary-scan environment Lattice Semiconductor's ispVM System. Lattice's ispVM System is a programming engine that supports the IEEE-1532 standard for in-system device configuration.
Accellera legt Roadmap für 2005 vor
News & Analysis  
2/14/2005   Post a comment
Die Systembeschreibungssprache 'SystemVerilog' steht unter der Federführung des IEEE. Das hält die Standardisierungsorganisation Accellera nicht davon ab, eine Accellera-Roadmap für 2005 vorzulegen. Die Industrievereinigung hat sich für das laufende Jahr vorgenommen, die Kompatibilität der Open Verification Library (OVL) und der Programmiersprache AMS zu SystemVerilog zu verbessern.
Users laud C design in DAC 'trip report'
News & Analysis  
2/14/2005   Post a comment
Engineers are warming to C language design tools, according to reviews in the Design Automation Conference (DAC) "trip report" released Friday (Feb. 11) by industry gadfly John Cooley. In the report, 368 engineers provided detailed reviews of chip design tools from dozens of vendors.
Web downloadable programmable logic design tool suite supports new low-cost LatticeEC FPGAs
Product News  
2/11/2005   Post a comment
Complete programmable design tool solution intended for initial technology evaluation, students and other programmable logic users who require low- to medium-scale integration.
Spice simulator available at Fry's Electronics
News & Analysis  
2/10/2005   Post a comment
Opening a new and unexpected channel for EDA product distribution, Intusoft has started selling its ICAP/4 Consumer Spice simulation product through superstore Fry's Electronics. Consumers can walk into any of the 28 Fry's outlets and buy the product for $249.
Real Intent raises $6M, expands team
News & Analysis  
2/10/2005   Post a comment
Formal verification provider Real Intent Inc. has closed a new round of financing for $6.5 million, bringing the total invested in the company to $11.5 million. The company also announced an expanded executive team and a broader product focus.
IP reuse requires a verification strategy
News & Analysis  
2/9/2005   Post a comment
Silicon intellectual property (IP) reuse won't work unless you can verify the IP, says Denali's Sean Smith. Drawing on his experience as a designer, he shows why you need a verification plan and how you can use verification IP.
Will China beat the U.S. in verification?
News & Analysis  
2/7/2005   Post a comment
What's needed is a top-down verification environment that starts with the specification, says consultant Brian Bailey. If inertia prevents that from happening here, it may happen elsewhere.
DATE 2005 met l’accent sur les systèmes embarqués
News & Analysis  
2/7/2005   Post a comment
Le compte à rebours est lancé. Du 7 au 11 mars 2005, la conférence DATE (Design Automation and Test in Europe) rassemblera en son sein concepteurs, technologues et grands dirigeants de la sphère électronique internationale pour une approche critique des tendances et défis actuels en matière de systèmes embarqués.
Free chip estimation tool debuts online
News & Analysis  
2/7/2005   Post a comment
EDA startup Giga Scale Integration Corp. (GigaScale IC) has launched a free online version of InCyte, its chip estimation tool.
Cadence teams with China IC maker for SCDMA transceiver
News & Analysis  
2/4/2005   Post a comment
Cadence Design Systems Inc. said a Chinese partner has begun sampling a dual-mode RF transceiver designed using Cadence design platforms.
Programmierbare Chips laufen ASICs den Rang ab
Product News  
2/4/2005   Post a comment
Schlechte Zeiten für die EDA-Industrie: Die Anzahl der ASIC-Designs ist rückläufig, der Umstieg auf kleinere Halbleiterstrukturen läuft nicht so schnell wie erwartet. Die gute Nachricht: Plattform-orientierte Designs und programmierbare Chips sind im Kommen - als Vorboten eines neuen Innovationsschubs.
Cadence überrascht mit Restrukturierung – und neuer Technik
Product News  
2/4/2005   Post a comment
Gestützt von einem guten Geschäft im vierten Quartal, startet Cadence Design Systems, einer der wichtigsten Anbieter von Software für das Chip-Design, in das neue Jahr. Cadence plant einen organisatorischen Umbau des Unternehmens – und ein Geheimprojekt für "Manufacture-Aware"-Designs. Der Umbau allerdings kostet Arbeitsplätze.
Page 1 / 2   >   >>


Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Want to Present a Paper at ESC Boston 2015?
Max Maxfield
8 comments
I tell you, I need more hours in each day. If I was having any more fun, there would have to be two of me to handle it all. For example, I just heard that I'm going to be both a speaker ...

Martin Rowe

No 2014 Punkin Chunkin, What Will You Do?
Martin Rowe
Post a comment
American Thanksgiving is next week, and while some people watch (American) football all day, the real competition on TV has become Punkin Chunkin. But there will be no Punkin Chunkin on TV ...

Rich Quinnell

Making the Grade in Industrial Design
Rich Quinnell
13 comments
As every developer knows, there are the paper specifications for a product design, and then there are the real requirements. The paper specs are dry, bland, and rigidly numeric, making ...

Martin Rowe

Book Review: Controlling Radiated Emissions by Design
Martin Rowe
1 Comment
Controlling Radiated Emissions by Design, Third Edition, by Michel Mardiguian. Contributions by Donald L. Sweeney and Roger Swanberg. List price: $89.99 (e-book), $119 (hardcover).