Firms partner on PCIe verification News & Analysis 2/28/2006 Post a comment PLDApplications and EVE have forged a partnership whereby, PLDA's x4 PCIe Xpress intellectual property will be embedded in EVE's ZeBu hardware-assisted verification platform.
SystemC IDE requires no license for executables creation News & Analysis 2/28/2006 Post a comment Electronic system level and hardware description language design solution provider Summit Design said its Vista integrated development environment for SystemC design and debug can now easily create and compile executables of SystemC designs based on the OSCI simulation kernel.
Silicon Design Chain claims methodology validation News & Analysis 2/28/2006 Post a comment The Silicon Design Chain Initiative claimed that a second, enhanced version of its power-management methodology and implementation up to tapeout of the ARM 1136JF-S processor is proof of the methodology and its interdependent technologies.
Sparks fly at Cooley's 'Bigwig' panel News & Analysis 2/24/2006 Post a comment Sparks flew at Deepchip.com moderator John Cooley's annual "Bigwig" panel at the Design & Verification Conference (DVCon), with representatives from smaller companies suggesting that pricing strategies by the larger companies were hurting the overall EDA market.
Sequence revamps Columbus-AMS News & Analysis 2/23/2006 Post a comment Sequence Design released the next generation of Columbus-AMS, described by the company as both a foundation for its RTL-to-silicon power-aware design tools and the industry's premier RLC parasitic extraction tool for high-performance, analog/mixed-signal design
Xilinx, ISR offering SDR kit News & Analysis 2/22/2006 Post a comment Xilinx and ISR Technologies released an off-the-shelf prototyping-to-production kit that the companies say accelerates implementation of software defined radio modems.
Analysis: Fresh fixes for industry's RET addiction News & Analysis 2/20/2006 Post a comment A wave of products with launches timed to coincide with the SPIE Microlithography Conference promise to provide the semiconductor industry with new ways to implement the resolution enhancement technologies to which it is addicted.
How much test compression is enough? Design How-To 2/20/2006 Post a comment Scan compression is necessary, but you can reach a point of diminishing returns with test data volume reduction (TDVR), says Synopsys' Chris Allsup. This article shows you how to determine what you really need.
Tanner's T-Spice supports PSP model News & Analysis 2/17/2006 Post a comment Tanner EDA said the newest version of its T-Spice Pro Circuit Simulator program for analog and mixed-signal IC design supports the Penn State Philips model, the new industry standard CMOS transistor model selected by the Compact Model Council in December to replace BSIM3 and BSIM4.
Synopsys stock climbs following earnings News & Analysis 2/17/2006 Post a comment Shares of Synopsys climbed 61 cents, or nearly 2.8 percent, closing at $22.62 one day after the company posted a $1.7 million fourth quarter profit, showing revenue growth for the fifth consecutive quarter.
Modeling suite includes SysML solution News & Analysis 2/17/2006 Post a comment Artisan Software Tools has launched the latest version of its Artisan Studio suite of UML modeling tools, including an out-of-the-box solution for Systems Modeling Language requirements modeling.
Mentor says Calibre mask data prep ready for 45 nm News & Analysis 2/16/2006 Post a comment Mentor Graphics said its Calibre MDP photomask data preparation suite has been qualified for production at leading integrated device manufacturers for the 45-nanometer process technology in flows based on the Oasis file format, the heir apparent to GDSII.
Quadros dual-mode RTOS ports to Freescale’s Coldfire MPUs Product News 2/14/2006 Post a comment Quadros Systems, Inc. is porting its RTXC dual-mode RTOS to the Freescale ColdFire MCF532x and MCF537x processors. With the convergent capabilities of the RTOS, developers can optimize both the dataflow and control characteristics of the Freescale processor family.
Emulation startup gets $6 million in funding News & Analysis 2/14/2006 Post a comment French emulation startup EVE announced the closing of a $6 million C round of funding from existing investors Auriga Partners, 3i, CAPE , Siparex Ventures and Edmond de Rothschild Venture Capital Management.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.