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Content tagged with Design Tools (EDA)
posted in February 2006
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Jury finds Mohsen guilty of perjury, obstruction of justice
News & Analysis  
2/28/2006   Post a comment
A federal jury here has found former Aptix Corp. CEO Amr Mohsen guilty of 14 counts, including perjury, mail fraud and obstruction of justice in connection with a 2000 patent dispute.
Power analysis tool suite adds SystemVerilog support
News & Analysis  
2/28/2006   Post a comment
Sequence Design released the next generation of its PowerTheater design suite, targeting requirements for wireless, mobile, and large system-on-chip designs below the 90 nanometer node.
Firms partner on PCIe verification
News & Analysis  
2/28/2006   Post a comment
PLDApplications and EVE have forged a partnership whereby, PLDA's x4 PCIe Xpress intellectual property will be embedded in EVE's ZeBu hardware-assisted verification platform.
Cypress offering eval kit for auto image sensor technology
Product News  
2/28/2006   Post a comment
Cypress Semiconductor introduced an evaluation kit for its automotive image sensor technology. The company said the kit enables designers to quickly develop automotive safety systems using Cypress's image sensor technology for various applications.
Online chip estimation tool claims 4,000 users
News & Analysis  
2/28/2006   Post a comment
Giga Scale Integration more than 22,000 IC designs have been estimated through ChipEstimate.com since its introduction. The company claims more than 4,000 individual users.
DSP development tools target Serial RapidI/O
Product News  
2/28/2006   Post a comment
Texas Instruments has launched its TMS320C6455 DSP evaluation module (EVM) and a TMS320C6455 DSP developers starter kit (DSK), both with a Serial RapidIO (sRIO) bus interface.
SystemC IDE requires no license for executables creation
News & Analysis  
2/28/2006   Post a comment
Electronic system level and hardware description language design solution provider Summit Design said its Vista integrated development environment for SystemC design and debug can now easily create and compile executables of SystemC designs based on the OSCI simulation kernel.
Silicon Design Chain claims methodology validation
News & Analysis  
2/28/2006   Post a comment
The Silicon Design Chain Initiative claimed that a second, enhanced version of its power-management methodology and implementation up to tapeout of the ARM 1136JF-S processor is proof of the methodology and its interdependent technologies.
Firms tout low-power, 90-nm Common Platform flows
News & Analysis  
2/27/2006   Post a comment
EDA heavyweights Cadence Design Systems, Synopsys and Magma Design Automation each announced low-power, 90-nanometer reference flows for the IBM-Chartered Semiconductor Manufacturing common manufacturing platform.
Mentor to offers $175 million in debt
News & Analysis  
2/27/2006   Post a comment
Mentor Graphics plans to offer a private placement of $175 million of convertible subordinated debentures due in 2026.
The 'what' and 'why' of transaction level modeling
Design How-To  
2/27/2006   Post a comment
Mentor Graphics' Bryan Bowyer covers the basics of transaction-level modeling, and shows how algorithmic synthesis can help with the signal processing portion of the design.
Trade association offering interconnect modeling standard
News & Analysis  
2/25/2006   Post a comment
The Government Electronics and Information Technology Association has created the IBIS Interconnect Modeling Specification to provide a universal method for representing interconnect modeling data for transfer between design and simulation tools.
Startup to name two VPs
News & Analysis  
2/25/2006   Post a comment
Power-focused EDA startup Azuro plans to announce the addition of Hazem Almusa and Ashutosh Mauskar to its management team.
Network-on-chip solution to support AMBA 3 AXI protocol
Product News  
2/24/2006   Post a comment
French network-on-chip solution startup Arteris plans to release the latest version of its Arteris NoC Solution, including support for the AMBA 3 AXI protocol from ARM.
Sparks fly at Cooley's 'Bigwig' panel
News & Analysis  
2/24/2006   Post a comment
Sparks flew at Deepchip.com moderator John Cooley's annual "Bigwig" panel at the Design & Verification Conference (DVCon), with representatives from smaller companies suggesting that pricing strategies by the larger companies were hurting the overall EDA market.
Optimality study of logic synthesis for LUT-based FPGAs
Programmable Logic DesignLine Blog  
2/23/2006   Post a comment
It looks like there are going to be a bumper crop of interesting papers presented at the FPGA 2006 conference this year.
Real Intent extends capabilities of clock tool
News & Analysis  
2/23/2006   Post a comment
EDA formal verification supplier Real Intent has extended the capabilities of its clock tool, Clock Intent Verification.
Technique proposed for improving direct-write throughput
News & Analysis  
2/23/2006   Post a comment
Japanese researchers proposed a new design technique for improving the throughput of maskless and quasi-maskless lithography tools for the production of devices in small quantities.
Sequence revamps Columbus-AMS
News & Analysis  
2/23/2006   Post a comment
Sequence Design released the next generation of Columbus-AMS, described by the company as both a foundation for its RTL-to-silicon power-aware design tools and the industry's premier RLC parasitic extraction tool for high-performance, analog/mixed-signal design
TI extends ASIC library support for third-party tools
Product News  
2/22/2006   Post a comment
Texas Instruments released version 5 of its Pyramid digital ASIC design kit, targeting telecommunications, consumer and wireless infrastructure markets.
Xilinx, ISR offering SDR kit
News & Analysis  
2/22/2006   Post a comment
Xilinx and ISR Technologies released an off-the-shelf prototyping-to-production kit that the companies say accelerates implementation of software defined radio modems.
Test software targets WiFi chipset
Product News  
2/22/2006   Post a comment
LitePoint releases production test software for CSR's UniFi WiFi Chipset
Magma, Rio Design ink OEM agreement
News & Analysis  
2/22/2006   Post a comment
Magma Design Automation will resell Rio Design Automation's software through an original equipment manufacturer agreement.
IEEE recognizes Synopsys engineers for SystemVerilog contributions
News & Analysis  
2/22/2006   Post a comment
IEEE has presented its Working Group Chairman's Award to two Synopsys technologists and certificates of recognition to 14 other Synopsys engineers for contributions to the development of the SystemVerilog standard.
Ample launches full IC design in Bangalore
News & Analysis  
2/22/2006   Post a comment
Fabless semiconductor company Ample Communications, whose Indian design center has so far focused on verification, will now work on complete designs of next-generations ICs.
eInfochips offering silicon, system validation
News & Analysis  
2/22/2006   Post a comment
Silicon and product design services firm eInfochips Inc. has begun offering pre- and post silicon validation, system validation and reference design services.
AMD researcher calls for design regularity
News & Analysis  
2/21/2006   Post a comment
Overcoming manufacturability challenges at the 45-nanometer node and beyond requires a migration to more "regular" design layouts, according to Luigi Capodieci of Advanced Micro Devices.
EDA software being sold by Walmart
News & Analysis  
2/20/2006   Post a comment
EDA vendor Aldec said its Active-HDL student edition is now available through the Walmart Online store and Barnes & Noble bookstores.
Aprio offers tool for both sides of DFM
News & Analysis  
2/20/2006   Post a comment
Aprio Technologies is set to introduce its first product intended for both the design and manufacturing communities, Halo-iOPC.
Brion applies focus exposure modeling to OPC
News & Analysis  
2/20/2006   Post a comment
Brion Technologies plans to introduce an OPC implementation tool built on the foundation of its Tachyon platform at the SPIE Microlithography conference.
Analysis: Fresh fixes for industry's RET addiction
News & Analysis  
2/20/2006   Post a comment
A wave of products with launches timed to coincide with the SPIE Microlithography Conference promise to provide the semiconductor industry with new ways to implement the resolution enhancement technologies to which it is addicted.
How much test compression is enough?
Design How-To  
2/20/2006   Post a comment
Scan compression is necessary, but you can reach a point of diminishing returns with test data volume reduction (TDVR), says Synopsys' Chris Allsup. This article shows you how to determine what you really need.
Tenison's VTOC supports VHDL, mixed languages
Product News  
2/20/2006   Post a comment
Electronic system level EDA vendor Tenison Design Automation announced VHDL and mixed Verilog/VHDL language support for its VTOC product.
French firm adds SystemVerilog assertion support to debug tool
Product News  
2/17/2006   Post a comment
French EDA and test automation provider Temento Systems plans to announce that the platform edition of its DialLite instrumentation and debug tool has added support for SystemVerilog assertions.
Letter: U.S. engineering not dead?
News & Analysis  
2/17/2006   Post a comment
A 44-year engineer sounds off on a recent article about a panel that suggested that engineering in the U.S. is alive and well.
Startup co-founder bound for SVEC Hall of Fame
News & Analysis  
2/17/2006   Post a comment
Thomas Kailath, co-founder of design-for-manufacturing startup Clear Shape Technologies, will be inducted into the Silicon Valley Engineering Council Hall of Fame.
Tanner's T-Spice supports PSP model
News & Analysis  
2/17/2006   Post a comment
Tanner EDA said the newest version of its T-Spice Pro Circuit Simulator program for analog and mixed-signal IC design supports the Penn State Philips model, the new industry standard CMOS transistor model selected by the Compact Model Council in December to replace BSIM3 and BSIM4.
Synopsys stock climbs following earnings
News & Analysis  
2/17/2006   Post a comment
Shares of Synopsys climbed 61 cents, or nearly 2.8 percent, closing at $22.62 one day after the company posted a $1.7 million fourth quarter profit, showing revenue growth for the fifth consecutive quarter.
Modeling suite includes SysML solution
News & Analysis  
2/17/2006   Post a comment
Artisan Software Tools has launched the latest version of its Artisan Studio suite of UML modeling tools, including an out-of-the-box solution for Systems Modeling Language requirements modeling.
Agilent claims simulation breakthrough for non-linear circuits
Product News  
2/16/2006   Post a comment
Agilent Technologies claimed a breakthrough in its core EDA frequency-domain simulation technology that it said provides crucial circuit performance information that can help avoid design errors.
Virtual platform supports TI’s OMAP3 processor
Product News  
2/16/2006   Post a comment
Virtio Corp.’s VPOM-3430 Virtual Platform, provides a complete simulated environment for TI’s OMAP3430 hardware and software. The OMAP3430 processor is the first member of TI’s OMAP 3 architecture.
Mentor says Calibre mask data prep ready for 45 nm
News & Analysis  
2/16/2006   Post a comment
Mentor Graphics said its Calibre MDP photomask data preparation suite has been qualified for production at leading integrated device manufacturers for the 45-nanometer process technology in flows based on the Oasis file format, the heir apparent to GDSII.
Synopsys posts profit, revenue growth
News & Analysis  
2/16/2006   Post a comment
Top-tier EDA vendor Synopsys reported a net income of $1.7 million on revenue of $260.2 million for the first quarter of its fiscal 2006, which closed Jan. 31.
MoSys doubles Q4 revenue, narrows net loss
News & Analysis  
2/15/2006   Post a comment
High-density embedded memory supplier Monolithic System Technology reported a GAAP net loss of $1.1 million on revenue of $2.4 million for the fourth quarter of 2005.
Chip designer eInfochips expands to Japan
News & Analysis  
2/15/2006   Post a comment
Chip designer eInfochips plans to set up a subsidiary company in Japan to tap what it says is a growing market there.
FPGA tool suite streamlines embedded system design
Product News  
2/15/2006   Post a comment
Xilinx's 8.1i version of the Platform Studio tool suite incorporates a new graphical user interface that is intended to streamline embedded processing design.
Ansoft quarterly earnings up 50 percent year-to-year
News & Analysis  
2/14/2006   Post a comment
EDA vendor Ansoft reported a net income in accordance with generally accepted accounting principles of $4.3 million for the third quarter of its fiscal 2006, up 50 percent year-to-year.
Quadros dual-mode RTOS ports to Freescale’s Coldfire MPUs
Product News  
2/14/2006   Post a comment
Quadros Systems, Inc. is porting its RTXC dual-mode RTOS to the Freescale ColdFire MCF532x and MCF537x processors. With the convergent capabilities of the RTOS, developers can optimize both the dataflow and control characteristics of the Freescale processor family.
Emulation startup gets $6 million in funding
News & Analysis  
2/14/2006   Post a comment
French emulation startup EVE announced the closing of a $6 million C round of funding from existing investors Auriga Partners, 3i, CAPE , Siparex Ventures and Edmond de Rothschild Venture Capital Management.
RFIC and system-design simulators link
Product News  
2/14/2006   Post a comment
Xpedion Design Systems, Inc. announced an interface to Simulink from The MathWorks to couple system-level and transistor-level simulation for RF design.
Page 1 / 2   >   >>


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