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Content tagged with Design Tools (EDA)
posted in February 2007
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EDA vendors unveil SoC design trimmers
Product News  
2/28/2007   Post a comment
EDA vendors announce new software tools that streamline the system-on-chip (SoC) design cycle and the semiconductor verification process.
Tools reduce clock tree power by 25%, Magma claims
Product News  
2/28/2007   Post a comment
Magma Design Automation introduced a pair of low-power IC implementation and analysis tools that the company claims have been shown to reduce power consumption in nanometer ICs by 25 percent.
MathStar and Mentor announce partnership for FPOA design tools
Product News  
2/27/2007   Post a comment
MathStar and Mentor have teamed to deliver design tools for use with mathStar's Field Programmable Object Array (FPOA) devices.
PSoC Express design tool supports capacitive sensing interface
Product News  
2/27/2007   Post a comment
Cypress Semiconductor's latest version of its PSoC (Programmable System on Chip) Express development tool, 2.2, supports CapSense capacitive sensor technology, as well as its WirelessUSB LP 2.4-GHz radio-on-a-chip.
Cypress tool adds support for capacitive sensing
Product News  
2/27/2007   Post a comment
Cypress Semiconductor rolled out version 2.2 of the company's PSoC Express development tool for programmable system-on-chip mixed-signal arrays. The new release adds support for Cypress's CapSense capacitive sensing solution and the company's WirelessUSB LP 2.4-GHz wireless radio-on-a-chip.
DaVinci platform speeds digital video product development
Product News  
2/26/2007   Post a comment
Aimed at accelerating digital video product development, TI has launched a $500 development platform for its DaVinci DM643x series processors that are designed with a DSP core.
DVCon: lessons for managers too
Blog  
2/26/2007   Post a comment
DVCon 2007 was a success, and its sponsoring consortium, Accellera, will be very pleased with the results. Yet, as with all conferences, some things went better than others. So here are the highlights and lowlights of the conference.
System simulation speeds application development
Design How-To  
2/26/2007   Post a comment
Developing applications for a wide range of mobile terminals can be a major headache for software engineers. System simulation now provides a way to develop and test software running on a virtual platform long before the hardware is available. Mark Snook explains.
IC design: Brion tunes Tachyon OPC for post-45-nm era
News & Analysis  
2/26/2007   Post a comment
Brion Technologies Inc. this week will roll out the second generation of its computational lithography technology, the Tachyon 2.0 hardware-assisted optical proximity correction (OPC) solution. Brion claims the product has the accuracy and throughput required for OPC in designs at 45 nanometers and below.

EDA CEOs predict strong 2007
News & Analysis  
2/24/2007   Post a comment
2007 should be another good year for the EDA industry, according to CEOs who spoke at the EDA Consortium's annual forecast panel Feb. 22. Most declined to offer specific numbers, however.
Sparks fly at EDA 'troublemakers' panel
News & Analysis  
2/23/2007   Post a comment
EDA vendor representatives debated low-power standards, Cadence's Skill language, outsourcing to India, and other hot topics at a "Troublemakers" DVCon panel organized by industry gadfly John Cooley.
Accellera approves UPF power format
News & Analysis  
2/22/2007   Post a comment
The Accellera standards organization has approved a 1.0 draft of the Unified Power Format (UPF), and is participating in attempts to converge it with the Cadence Design Systems backed Common Power Format.
DVCon keynote: Verification takes a broader view
News & Analysis  
2/22/2007   Post a comment
IC verification must look beyond languages and engines and embrace an "enterprise level" methodology that includes hardware and software, said Cadence Design Systems' Moshe Gavrielov, keynote speaker at the DVCon Conference.
An Enterprise-wide Approach Accelerates Next-Generation System-level Development
Blog  
2/22/2007   Post a comment
As the market moves from 65nm- to 45nm-based SoCs and beyond towards full system-level design and development, we must be extremely careful not to let hardware and software development continue on such disjointed paths. We must leverage many of today's proven verification process automation capabilities for hardware testing and apply them towards the next-generation hardware/software design and implementation processes.
How to use M and Simulink for DSP control and datapath design
Design How-To  
2/21/2007   Post a comment
This tutorial discusses the tradeoffs of abstraction versus implementability and highlights an approach of embedding M into Simulink to gain some of the advantages of both.
Synopsys Q1 revenue up 15 percent
News & Analysis  
2/21/2007   Post a comment
Synopsys posted revenue of $300 million for its first fiscal quarter ending Jan. 31, 2007. a 15 percent gain compared to the prior year quarter.
Blaze DFM merges with Aprio
News & Analysis  
2/21/2007   Post a comment
Blaze DFM has announced that it's merging with fellow design for manufacturability (DFM) startup Aprio Technologies, which experienced difficulties and layoffs last year. The merged company promises a comprehensive "electrical" DFM solution.
French ESL firm scores first-round funding
News & Analysis  
2/19/2007   Post a comment
French electronic system level (ESL) tool provider CoFluent Design has raised $2.6 million in first-round venture capital funding, and will seek to expand its marketing worldwide.
New EDA Tools Improve Low Power Design
Design How-To  
2/19/2007   Post a comment
Despite tightening power requirements, few chip designers have the tools and techniques in place to meet their budgets. This article describes new tools and techniques, as well as some promising capabilities which could be delivered in future EDA offerings.
Is DFM all talk?
Blog  
2/19/2007   Post a comment
Not a week goes by without a panel, a viewpoint, or an analysis of DFM and the DFM market. This brings to my mind some fundamental questions. If DFM is so necessary, why the debate? If every design team needs DFM why the uncertainty about DFM startups viability? And can we all agree to one definition of DFM?
Synplicity's complete design solution for Xilinx Virtex-5 SXT DSP FPGAs
Product News  
2/16/2007   Post a comment
The combination of the Synplify Pro synthesis engine and Synplify DSP provides optimal results for new Xilinx Virtex-5 SXT DSP FPGAs.
Altium showcases new NanoBoard-NB2
Product News  
2/16/2007   Post a comment
Altium's NanoBoard-NB2 provides a hardware platform on which to implement/debug embedded designs targeted to a wide range of processor and FPGA architectures.
Carbon Design Systems to provide hardware-software profiling webinar
News & Analysis  
2/16/2007   Post a comment
Ideal for design engineers, architects, and managers, the hardware-software profiling webinar will be held on Tuesday, February 27, 2007, 11:00 am PST / 2:00 pm EST
Commentary: Liberating the Liberty library format
News & Analysis  
2/16/2007   Post a comment
The open-source Liberty library format is owned and controlled by a single vendor, and should be owned by a public consortium such as Accellera or the IEEE, argues Magma Design Automation's Kam Kittrell.
Open-source libraries boost SystemVerilog
Product News  
2/15/2007   Post a comment
Free, open-source verification libraries developed by consultant Mike Mintz provide a set of common building-block utilities and define a methodology for SystemVerilog users.
Mathematical package helps in circuit design
Design How-To  
2/15/2007   Post a comment
Using a mathematical package to help with the evaluation of the operatring characteristics of a circuit can save significant development time and increase manufacturability and yield.
Custom layout editor automates DFM
Product News  
2/14/2007   Post a comment
Claiming a new level of automation for design for manufacturability (DFM), Silicon Canvas has added built-in features to its Laker custom IC layout editor that support foundry DFM rules.
Statistical tool targets analog, custom ICs
Product News  
2/12/2007   Post a comment
Startup Solido Design Automation is disclosing technology that will bring transistor-level statistical design and verification to analog and custom IC designers.
OneSpin's equivalence checker for advanced FPGA design verification
Product News  
2/12/2007   Post a comment
360 EC-FPGA is the first equivalence checker to support all sequential optimizations performed by FPGA synthesis tools on large designs.
Jumping over verification model hurdles
Blog  
2/12/2007   Post a comment
Freely available models of IP can simplify market dynamics, improve quality of verification, and may even introduce a new type of open source community.
Achieving completeness in IP functional verification
Design How-To  
2/12/2007   Post a comment
This article formalizes the concept of best possible verification quality -- completeness -- and describes a methodology, field-proven on many complex module and intellectual property (IP) designs, that tells you when verification is complete.
Mentor Graphics Delivers Next Generation Board Station Flow
Product News  
2/9/2007   Post a comment
Mentor Graphics Corporation announced the release of Board Station XE, the next generation version of its Board Station design flow for large, enterprise customers.
EDA notables join ChipVision TAB
News & Analysis  
2/9/2007   Post a comment
EDA luminaries Raul Camposano, Jason Cong, and Jim Hogan have joined a new technical advisory board (TAB) set up by ChipVision, a provider of low-power design tools.
Video color space converter design using mixed-signal via-configurable ASICs
Design How-To  
2/9/2007   Post a comment
Mixed-signal via-configurable ASIC technology gives designers the ability to develop fully integrated mixed-signal ASICs without the lengthy development cycles, high NREs, high risk, and extended fabrication times associated with full-custom mixed-signal IC development. Designing a complete video color space converter becomes easier, for example, with mixed-signal via-configurable ASIC.
Management kit integrates multiple system functions into MCU
Product News  
2/9/2007   Post a comment
Microchip has developed the PICDEM System Management kit that integrates common functions, such as a dedicated Real-Time Clock (RTC), serial EEPROM, thermal-management, analog-to-digital converter (ADC) and power sequencing into a single PIC microcontroller.
Conference puts IC routing to the test
News & Analysis  
2/8/2007   Post a comment
Aiming to improve IC routing technology, the International Symposium on Physical Design (ISPD) is initiating a routing contest at this year's meeting, planned for March 18-21 in Austin, Texas. ISPD has also announced the technical program.
Achieving Timing Convergence
Design How-To  
2/8/2007   Post a comment
Each new generation of FPGAs has given us higher performance and higher capacity. Designs have become larger and more complex; containing many clock domains, use of embedded multiply accumulation functions, embedded processors and a variety of memory resources. These changes have help propel FPGAs into many new applications. At the same time, predictability of timing in a Synthesis/Place and Route flow has degraded with each generation.
Zuken upgrades free PCB CAD tool
Product News  
2/8/2007   1 comment
The latest version of Cadstar Express, Zuken's limited-capacity but free pc-board CAD solution, claims to provide all the latest features of the commercial Cadstar 9.0 release.
Ramtron adds USB interface to 8051 MCU development kit
Product News  
2/7/2007   Post a comment
In an effort to expedite programming and improve in-circuit debugging, Ramtron International Corp. is offering a universal serial bus (USB) based JTAG interface with its Versa 8051 microcontroller development tools.
Macro modeling supports voltage drop analysis
Product News  
2/6/2007   Post a comment
Sequence Design has introduced a new approach to modeling memories and other macros for IC voltage drop analysis, and has upgraded its CoolTime analysis and optimization solution.
Lithography pioneer wins IEEE's highest honor
News & Analysis  
2/6/2007   Post a comment
Stanford emeritus professor Thomas Kailath, a pioneer of IC lithography techniques and a founder of Clear Shape Technologies, is the recipient of the IEEE's annual Medal of Honor award.
DesignCon Morsels
Blog  
2/6/2007   Post a comment
The DesignCon conference provided opportunities for thought, learning, and analysis. It also showed that we have yet to solve important problems in methods and training that have faced us for some time.
Bluespec sets new direction for IP design and reuse
News & Analysis  
2/5/2007   Post a comment
Bluespec's AzureIP Foundation Library of composable, self-documenting IP provides ESL capabilities that accelerate development and verification.
Reducing FPGA Compile Time Using Parallel Compilation Methodology
Design How-To  
2/5/2007   Post a comment
Parallel Compilation and incremental design techniques help reduce development time when targeting complex FPGS devices.
Commentary: How ESL can regain credibility
News & Analysis  
2/2/2007   Post a comment
Electronic system level (ESL) design has lost credibility because of unrealistic expectations, says Chad Spackman, CTO of ESL startup CebaTech. He presents a set of "achievable" goals.
Mentor revenues up, Synplicity flat
News & Analysis  
2/2/2007   Post a comment
Mentor Graphics Corp. 2006 revenue is up 12 percent over 2005, but fellow EDA vendor Synplicity Inc. had virtually flat revenue growth for the quarter and the year, according to earnings releases posted Thursday (Feb. 1).
Panelists: Front-end design needs overhaul
News & Analysis  
2/2/2007   Post a comment
IC design flows have improved in the past decade, but more work is needed to bring concerns such as power into the flow earlier, said panelists at the DesignCon conference Wednesday (Jan. 31).
CEO resigns as Celoxica shifts focus
News & Analysis  
2/1/2007   Post a comment
Celoxica CEO Phil Bishop has resigned as the company shifts its primary focus from electronic system level (ESL) design to accelerated computing. The search is underway for a replacement.
Patent ruling aids defense, Magma says
News & Analysis  
2/1/2007   Post a comment
A ruling that two patents are jointly owned by Synopsys and IBM will aid Magma Design Automation's defense, the company says. But Synopsys still plans to pursue infringement claims.
Freescale opts for AMS kit from Cadence
News & Analysis  
2/1/2007   Post a comment
The kit leverages key capabilities of advanced AMS technologies, flows, and methodologies and is one of several Cadence kits.
Page 1 / 2   >   >>


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