Cypress tool adds support for capacitive sensing Product News 2/27/2007 Post a comment Cypress Semiconductor rolled out version 2.2 of the company's PSoC Express development tool for programmable system-on-chip mixed-signal arrays. The new release adds support for Cypress's CapSense capacitive sensing solution and the company's WirelessUSB LP 2.4-GHz wireless radio-on-a-chip.
DVCon: lessons for managers too Blog 2/26/2007 Post a comment DVCon 2007 was a success, and its sponsoring consortium, Accellera, will be very pleased with the results. Yet, as with all conferences, some things went better than others. So here are the highlights and lowlights of the conference.
System simulation speeds application development Design How-To 2/26/2007 Post a comment Developing applications for a wide range of mobile terminals can be a major headache for software engineers. System simulation now provides a way to develop and test software running on a virtual platform long before the hardware is available. Mark Snook explains.
IC design: Brion tunes Tachyon OPC for post-45-nm era News & Analysis 2/26/2007 Post a comment Brion Technologies Inc. this week will roll out the second generation of its computational lithography technology, the Tachyon 2.0 hardware-assisted optical proximity correction (OPC) solution. Brion claims the product has the accuracy and throughput required for OPC in designs at 45 nanometers and below.
EDA CEOs predict strong 2007 News & Analysis 2/24/2007 Post a comment 2007 should be another good year for the EDA industry, according to CEOs who spoke at the EDA Consortium's annual forecast panel Feb. 22. Most declined to offer specific numbers, however.
Sparks fly at EDA 'troublemakers' panel News & Analysis 2/23/2007 Post a comment EDA vendor representatives debated low-power standards, Cadence's Skill language, outsourcing to India, and other hot topics at a "Troublemakers" DVCon panel organized by industry gadfly John Cooley.
Accellera approves UPF power format News & Analysis 2/22/2007 Post a comment The Accellera standards organization has approved a 1.0 draft of the Unified Power Format (UPF), and is participating in attempts to converge it with the Cadence Design Systems backed Common Power Format.
DVCon keynote: Verification takes a broader view News & Analysis 2/22/2007 Post a comment IC verification must look beyond languages and engines and embrace an "enterprise level" methodology that includes hardware and software, said Cadence Design Systems' Moshe Gavrielov, keynote speaker at the DVCon Conference.
An Enterprise-wide Approach Accelerates Next-Generation System-level Development Blog 2/22/2007 Post a comment As the market moves from 65nm- to 45nm-based SoCs and beyond towards full system-level design and development, we must be extremely careful not to let hardware and software development continue on such disjointed paths. We must leverage many of today's proven verification process automation capabilities for hardware testing and apply them towards the next-generation hardware/software design and implementation processes.
Blaze DFM merges with Aprio News & Analysis 2/21/2007 Post a comment Blaze DFM has announced that it's merging with fellow design for manufacturability (DFM) startup Aprio Technologies, which experienced difficulties and layoffs last year. The merged company promises a comprehensive "electrical" DFM solution.
New EDA Tools Improve Low Power Design Design How-To 2/19/2007 Post a comment Despite tightening power requirements, few chip designers have the tools and techniques in place to meet their budgets. This article describes new tools and techniques, as well as some promising capabilities which could be delivered in future EDA offerings.
Is DFM all talk? Blog 2/19/2007 Post a comment Not a week goes by without a panel, a viewpoint, or an analysis of DFM and the DFM market. This brings to my mind some fundamental questions. If DFM is so necessary, why the debate? If every design team needs DFM why the uncertainty about DFM startups viability? And can we all agree to one definition of DFM?
Custom layout editor automates DFM Product News 2/14/2007 Post a comment Claiming a new level of automation for design for manufacturability (DFM), Silicon Canvas has added built-in features to its Laker custom IC layout editor that support foundry DFM rules.
Achieving completeness in IP functional verification Design How-To 2/12/2007 Post a comment This article formalizes the concept of best possible verification quality -- completeness -- and describes a methodology, field-proven on many complex module and intellectual property (IP) designs, that tells you when verification is complete.
EDA notables join ChipVision TAB News & Analysis 2/9/2007 Post a comment EDA luminaries Raul Camposano, Jason Cong, and Jim Hogan have joined a new technical advisory board (TAB) set up by ChipVision, a provider of low-power design tools.
Video color space converter design using mixed-signal via-configurable ASICs Design How-To 2/9/2007 Post a comment Mixed-signal via-configurable ASIC technology gives designers the ability to develop fully integrated mixed-signal ASICs without the lengthy development cycles, high NREs, high risk, and extended fabrication times associated with full-custom mixed-signal IC development. Designing a complete video color space converter becomes easier, for example, with mixed-signal via-configurable ASIC.
Conference puts IC routing to the test News & Analysis 2/8/2007 Post a comment Aiming to improve IC routing technology, the International Symposium on Physical Design (ISPD) is initiating a routing contest at this year's meeting, planned for March 18-21 in Austin, Texas. ISPD has also announced the technical program.
Achieving Timing Convergence Design How-To 2/8/2007 Post a comment Each new generation of FPGAs has given us higher performance and higher capacity. Designs have become larger and more complex; containing many clock domains, use of embedded multiply accumulation functions, embedded processors and a variety of memory resources. These changes have help propel FPGAs into many new applications. At the same time, predictability of timing in a Synthesis/Place and Route flow has degraded with each generation.
Zuken upgrades free PCB CAD tool Product News 2/8/2007 1 comment The latest version of Cadstar Express, Zuken's limited-capacity but free pc-board CAD solution, claims to provide all the latest features of the commercial Cadstar 9.0 release.
DesignCon Morsels Blog 2/6/2007 Post a comment The DesignCon conference provided opportunities for thought, learning, and analysis. It also showed that we have yet to solve important problems in methods and training that have faced us for some time.
Mentor revenues up, Synplicity flat News & Analysis 2/2/2007 Post a comment Mentor Graphics Corp. 2006 revenue is up 12 percent over 2005, but fellow EDA vendor Synplicity Inc. had virtually flat revenue growth for the quarter and the year, according to earnings releases posted Thursday (Feb. 1).
CEO resigns as Celoxica shifts focus News & Analysis 2/1/2007 Post a comment Celoxica CEO Phil Bishop has resigned as the company shifts its primary focus from electronic system level (ESL) design to accelerated computing. The search is underway for a replacement.
Patent ruling aids defense, Magma says News & Analysis 2/1/2007 Post a comment A ruling that two patents are jointly owned by Synopsys and IBM will aid Magma Design Automation's defense, the company says. But Synopsys still plans to pursue infringement claims.
Blog Doing Math in FPGAs Tom Burke 2 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...