Scaling methods apply to EUV, says IMEC litho chief News & Analysis 2/27/2009 Post a comment Techniques being used to extend the life of 193-nm lithography appear equally applicable to next-generation extreme ultraviolet lithography, which could greatly increase the extendibility of the technology, according to Kurt Ronse, director of the advanced lithography program at nanoelectronics research center IMEC.
What is source-mask optimization? News & Analysis 2/27/2009 Post a comment A war of words of sorts emerged at the SPIE Advanced Lithography conference among vendors developing source-mask optimization tools in hopes of extending 193-nm immersion lithography to the 22-nm node.
Mentor posts profit, but will cut jobs News & Analysis 2/26/2009 Post a comment EDA vendor Mentor Graphics posted a profit of $31.5 million on revenue of $242.6 million for the quarter ended Jan. 31, in line with a revenue warning the company issued earlier this month. The company said it plans to cut an unspecified number of jobs as it trims costs amid the economic downturn.
Viewpoint: More to IP reuse than software tweaks Design How-To 2/25/2009 1 comment Platform-based design with heavy IP reuse will continue to proliferate as more functionality is included into tomorrow's chip, but differentiation through software alone falls short of power and performance requirements.
Software tool automates ECU software checks Product News 2/24/2009 Post a comment Automotive realtime networking expert TTTech Automotive (Vienna) has announced a software tool to validate the consistency of Autosar components in electronic control units (ECUs). TTX-Autoverify increases the engineering efficiency during system integration and thus helps to reduce time-to-market and costs, the vendor claims.
Low power verification methodology manual available News & Analysis 2/23/2009 Post a comment The Verification Methodology Manual for Low Power, a collaborative effort between ARM Holdings, Renesas Technology and Synopsys to document a methodology for the comprehensive verification of low power designs, is now available, Synopsys said.
Freescale's Su: Simplify DFM News & Analysis 2/23/2009 Post a comment During a keynote address at the SPIE Advanced Lithography conference, Lisa Su, senior vice president and general manager of networking and multimedia and chief technology officer for Freescale Semiconductor, asked the EDA and lithography communities for help in reigning in spiraling design complexity.
SpringSoft to buy functional qualification startup News & Analysis 2/23/2009 Post a comment Taiwanese EDA vendor SpringSoft has signed a definitive agreement to acquire all outstanding shares of startup Certess, a maker of functional qualification software for the creation of SoCs and integration of intellectual property blocks. Financial details of the agreement were not disclosed.
Analysis: Will Synopsys take over the world? News & Analysis 2/20/2009 1 comment While competitors stumble amid the downturn, Synopsys is firing on all cylinders and beating analyst expectations with revenue and profit. Executives say Synopsys' financial strength will drive future marketshare gains. But do customers want an EDA market with one dominant player?
Apache, ST to collaborate on 45-, 32-nm challenges News & Analysis 2/20/2009 Post a comment EDA vendor Apache Design Solutions and chipmaker STMicroelectronics have expanded their existing business relationship and technical collaboration to address the upcoming power and noise challenges associated with 45- and 32-nm designs.
MAXIM lance son centre de design virtuel News & Analysis 2/19/2009 Post a comment Maxim Integrated Products et Transim Technology Corporation (Portland, Oregon) ont collaboré pour le lancement du centre de conception EE-Sim Design Center de Maxim qui utilise la technologie WebSIM de Transim.
Power-aware FPGA design (Part 3) Design How-To 2/17/2009 Post a comment This three-part article covers several aspects of FPGA power consumption; it also provides a new look at power dissipation numbers, and questions the traditional methods of estimating and measuring power.
SyEna project to bring automation to analog design News & Analysis 2/17/2009 Post a comment If the researchers involved in the SyEna project are on the right track, analog circuit design is heading for a quantum leap: The project will bring a higher degree of automation to analog design. The researchers promise less faults in the designs and thus more reliable chips.
LSI rolls multicore strategy Product News 2/17/2009 Post a comment LSI Corp. rolled out at the Mobile World Congress a new multicore strategy behind an upcoming family of chips targeting wireless infrastructure gear, mixing and matching its portfolio of cores and on-chip interconnects from recent acquisitions to create new standard products and ASIC offerings.
Behavioral Design Drives Low-Power Silicon Design How-To 2/16/2009 Post a comment Using high level synthesis, a design team can implement and verify more functionality in hardware in less time than required for RTL design. This makes it feasible to move system functionality from software into dedicated hardware, reducing the number of instruction fetches and lowering required CPU clock speeds for significant system-level power savings.
We all need to pull together Programmable Logic DesignLine Blog 2/13/2009 Post a comment As usual, Mentor and Xilinx are both setting a really good example as to how big companies can help out and how we all need to pull together...
Video: Computer science meets the grid News & Analysis 2/13/2009 Post a comment Tomorrow's computers need to be designed to meet the energy efficiency needs of growing data centers and the power grid needs to evolve to be more like the Internet, according to Randy Katz, a professor of computer science speaking at an annual gathering of researchers from the University of California at Berkeley.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.