Formal verification set to play significant role in upcoming recovery Blog 2/26/2010 Post a comment As the recovery takes off, Jasper Design Automation said it is excited by the expanding role formal verification technology will play as IC design sizes continue to grow while market windows shrink. One of the facilitators of this paradigm is IP design and reuse, because now virtually all design starts are SoCs that could never be completed without internal and/or third-party IP.
Direct-write litho still facing uphill climb News & Analysis 2/26/2010 2 comments Multiple development efforts focused on e-beam direct-write lithography have reported progress this week at the SPIE Advanced Lithography conference. But, at least according to one prominent lithography researcher, production tools are still a minimum of five years away.
Magma provides EDA for Western China News & Analysis 2/25/2010 Post a comment Chengdu ICC (CDICC), a government-funded organization that promotes integrated circuit (IC) design in Chengdu, China, has opened an IC design center in cooperation with EDA software vendor Magma Design Automation Inc. (San Jose, Calif.).
Comment: ARM must beware the 'tied-selling' trap Blog 2/24/2010 1 comment The success of ARM Holdings plc with its series of low-power processing cores, and its relatively small-scale success - so far - with its Mali graphics processing cores puts ARM in a potentially dangerous position.
Comment: Sparking interest in engineering Industrial Control DesignLine Blog 2/23/2010 Post a comment Intel is behind a $3.5 billion initiative to support investment in U.S.-based growth-oriented industries. The initiative also wants to increase jobs available this year for recent college graduates.
DAC 2010 to award Richard Newton graduate scholarships News & Analysis 2/23/2010 Post a comment The 47th Design Automation Conference, to be held from June 13 to 18, 2010, in Anaheim, Calif., intends to award scholarships to promote graduate research and study in EDA and circuit design. These $24.000 scholarships are in honor of the memory of Dr. A. Richard Newton.
GateRocket rolls new version of FPGA debug tool Product News 2/23/2010 Post a comment FPGA verification and debug software vendor GateRocket Inc. Tuesday (Feb. 23) announced the newest version of its RocketVision debugging software, introducing new capabilities that allow designers to select individual design blocks to run in their simulator or GateRocket's RocketDrive hardware verification system.
Mentor Graphics to address variant diversity Product News 2/22/2010 Post a comment With the acquisition of Freescale's Virtual Garage software product line, EDA software vendor Mentor Graphics plans to address two aspect that increasingly complicate automotive electronic designer's work: First, the conflict between added value and costs associated with the complexity of multiple electronics options in cars. The second aspect is the availability of vehicle-specific design data to service workshops for instance dynamic circuit diagrams.
High-level synthesis, verification and language Design How-To 2/22/2010 2 comments The preferred high-level design methodology proceeds from high-level code to RTL code. Good verification practice requires that the input to High-level Synthesis (HLS) be verified first, via simulation (or some other analytical means), and then the output of HLS be verified, again via simulation or some other means. Using SystemC as the input language to HLS enables this flow, but using C as the HLS input language imposes a serious limitation on doing verification this way.
Scalable integration between OneSpin's ABV tool and Platform LSF Product News 2/22/2010 Post a comment EDA software vendor OneSpin Solutions GmbH (Munich, Germany) has presented the customizable integration between its 360 MV formal assertion-based verification (ABV) tool and Platform Computing's LSF infrastructure, a workload management solution for high performance computing (HPC) environments.
EDA chiefs hazard no guesses on 2010 market News & Analysis 2/20/2010 3 comments At the annual EDAC CEO panel, the leaders of EDA's biggest firms discussed trends impacting EDA growth, but left forecasts for the year to the panel's moderator, analyst Jay Vleeschhouwer.
Mentor names VP of new ventures News & Analysis 2/19/2010 1 comment Mentor Graphics Corp. announced it has named Serge Leef, current general manager of the System Level Engineering division, as vice president of New Ventures, to expand the company into markets adjacent to EDA.
ISSCC, Nvidia shortfall lead weekly story ranking News & Analysis 2/19/2010 Post a comment Here are the top five online stories for the week beginning Sunday, Feb. 14, as ranked by EE Times readers, up to and including Friday, Feb. 19. The ranking is based on the number of reader "views" or "hits" on a particular article.
Silicon Frontline enhances post-layout verification tools Product News 2/19/2010 Post a comment Startup Silicon Frontline Technology, Inc. has introduced the latest versions of its products for post-layout verification: F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices.
Tanner EDA, Sound Design Technologies develop PDKs Product News 2/18/2010 Post a comment Tanner EDA, a division of Tanner Research Inc. (Monrovia, Calif.), announced it has combined its specialized IC design software combined with integrated passives and chip-stacking technologies from Sound Design Technologies Ltd. (Ontario, Canada).
Analyst raises sales estimates for Altera News & Analysis 2/18/2010 Post a comment A technology research firm raised its estimates for Altera's 2010 and 2011 revenue, citing expectations of modest market share gains by the company against rivals in the programmable logic space.
TI's multicore SoC: Right notes, ringing hollow Signal Processing DesignLine Blog 2/17/2010 Post a comment While the new multicore system on chip (SoC) signal-processing architecture announced by Texas Instruments this week at Mobile World Congress hits all the right notes with respect to what's needed in next-generation basestation designs, it rings a bit hollow given how sketchy the architectural details remain when contrasted with more 'real' announcements from the likes of Freescale.
Reusable VHDL IP in the real world Design How-To 2/17/2010 3 comments
IP reuse is clearly a good thing. But in practice it has often proven surprisingly difficult to achieve. This article provides few principles and techniques that can be applied to make it more straightforward.
Help All of my simulations are passing! Blog 2/17/2010 Post a comment Pause and consider for a moment a world in which passing tests are not an indicator that all is well, but rather a warning flag that not enough functionality is being tested, vital checks that confirm proper operation of the design are missing, or problems in the verification infrastructure are masking test failures and hiding RTL bugs merrily making their way to fabrication.
EU project to define next gen design methodologies Product News 2/17/2010 Post a comment Scientists and companies from Europe and Brazil have joined forces in an EU-backed project that aims to develop design methods and EDA tools in a view to remove the limitations in physical implementation effectiveness associated with technology scaling and advanced sub-wavelength lithography.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.