Optimal team sizes for chip projects Blog 2/28/2011 Post a comment Chip design projects demand a threshold number of engineers to meet schedule targets, yet, there's a point at which adding resources yields little, if any, additional development throughput.
Evolution of manufacturing closure for advanced nodes (Part 2) Design How-To 2/28/2011 Post a comment Starting at the 40/45nm design node, DRC/DFM closure emerged as a significant new challenge to IC designers. No longer could manufacturing concerns be effectively handled with the traditional design-then-verify flow. This trend is expected to continue and worsen at the 32nm and 22nm nodes, where manufacturing closure may become a serious bottleneck in design schedules.
Report from EDSFair 2011 Blog 2/25/2011 Post a comment At this year's ESDFair, EVE SA (Palaiseau, France) conducted a survey to determine chip design and verification trends in Japan. Check out what attendees told EVE's booth staff!
Mentor beats estimates, eyes $1 billion mark News & Analysis 2/24/2011 5 comments EDA vendors Mentor Graphics and Magma Design Automation reported quarterly results that beat consensus analysts' expectations, with Mentor posting record annual revenue and saying it expects to become a $1 billion company in the current fiscal year.
Mentor claims comprehensive support for UVM 1.0 Product News 2/23/2011 Post a comment Mentor Graphics Corp. announced its comprehensive support for Accellera's Universal Verification Methodology (UVM) across a host of products including Questa advanced functional verification platform, the Questa MVC Verification IP library, the Veloce emulation platform and the Certe Testbench Studio tool.
Key factors for success in dealing with Asian fabs Design How-To 2/22/2011 6 comments This article is about managing relationships with Asian semiconductor foundries through the understating of the socio-business-cultural (SBC) environment. Since Taiwan, China, Singapore, South Korea and Malaysia host the major foundries, this article gives a good insight into the factors important for fabless/fablite companies to be successful.
Evolution of manufacturing closure for advanced nodes (Part 1) Design How-To 2/21/2011 Post a comment Manufacturing closure has become a key design challenge at smaller technology nodes such as 32 and 22nm. Starting at 45/40nm, the increasing complexity of design rule checks and design-for-manufacturing rules began to stress traditional physical design flows. This trend is expected to continue and worsen at the 32/22 nm nodes, where manufacturing closure may become a serious bottleneck in design schedules.
Let go of my Legos Blog 2/18/2011 12 comments Bill Neifert, Carbon's CTO, compares the design of today's SoCs with Lego bricks and outlines the analogies between the two seemingly disparate markets, from product strategy and development, product packaging and marketing to business models.
DATE 2011 is on track News & Analysis 2/16/2011 Post a comment DATE (Design, Automation & Test in Europe) 2011 is just around the corner, and due to the high demand, an additional exhibition space has been created for more than seventy exhibitors.
EDA focus shifts to system level design Design How-To 2/16/2011 Post a comment Companies designing complex electronics always face numerous challenges, which keep evolving, because each problem solved enables new advances that in turn lead to new challenges. The year ahead will see increased system engineering content in chip- and board-level designs.
The white screen of death... Blog 2/16/2011 27 comments I am not a happy person at the moment. The radiance of my smile is no longer lighting the world around me because earlier today, with no warning whatsoever, my computer gave up the ghost...
Ease production at 65nm with DFM Design How-To 2/16/2011 Post a comment The challenges of production at advanced process geometries are well-known. In anticipation of reaching today's leading-edge process nodes, EDA companies and chip foundries have been developing and perfecting DFM technology to address users' critical needs. However, many designers viewed these DFM tools with skepticism as they continued to get products to market without them.
MediaTek deploys Mentor's Calibre PERC News & Analysis 2/14/2011 Post a comment MediaTek Inc. announced it has licensed Calibre Programmable Electrical Rule Checker (PERC), Mentor Graphics' DFM solution designed to address advanced circuit verification to ensure optimal design yield and improve reliability.
EDA expert joins Oasys' board News & Analysis 2/14/2011 Post a comment EDA startup Oasys Design Systems Inc. announced it has named Gary Meyers, an experienced EDA and semiconductor executive, to its board of directors.
I want my own Jet Pack!!! Blog 2/12/2011 9 comments I know that the use of three exclamation marks (as in the title to this blog) is the sign of a deranged mind ... but I don’t care ... I want my own personal Jet Pack!!!
Insight EDA rolls ERC Analyzer Version 4.0 Product News 2/11/2011 Post a comment Insight EDA (Redwood City, Calif.) has released Version 4.0 of its Electrical Rule Checking (ERC) Analyzer. Aimed at mixed signal and mixed power designs, it will easily detect deeply buried domain crossing issues and help users avoid costly problems with silicon.
Standard design constraints: The next productivity boost for custom design Blog 2/11/2011 6 comments Manual design methodologies are no longer sufficient for custom designs as they begin to target 45nm-and-below process methodologies. Mark Waller, VP Engineering at Pulsic, Ltd., urges the custom-design community to work together and deliver a design constraints standard that will enable all custom design teams to maximize productivity gains.
Does EMC stand for exasperating, magic, or confusing?—Part 1 Design How-To 2/10/2011 10 comments While it is merely a nuisance to experience radio interference, it is definitely a serious matter if an ABS, stability control, or airbag suffers a malfunction because a vehicle passes a TV tower too closely. Thus, mastering EMC is a basic requirement for automotive electronics designers. Part one of this article explains basic strategies and provides useful hints.
MunEDA joins SI2 Initiative News & Analysis 2/10/2011 Post a comment MunEDA GmbH (Munich, Germany) announced it has joined the Silicon Integration Initiative (Si2) and the Si2's Open Process Design Kit Coalition (OPDKC).
Teaching an old dog (me) new tricks Blog 2/10/2011 24 comments Have you seen those things called ‘The Great Courses’? These are college-level courses that are available on DVD for you to study from the comfort of your sofa. I just ordered three...
Another activist investor targets Mentor News & Analysis 2/8/2011 5 comments Activist hedge fund Casablanca Capital has written a letter to Mentor Graphics' board of directors saying it will nominate a new slate of directors to the company's board after Mentor announced that it would hold its annual shareholder meeting on May 12, more than a month earlier than it was held in 2010.
So, what would you do? Blog 2/8/2011 1 comment Speaking of human mirrors, did you see…? And what about...? And you must have seen…! So what do you think you would do if you were ever faced with a situation like...?
STARC adopts Solido variability tool News & Analysis 2/8/2011 1 comment The Semiconductor Technology Academic Research Center (STARC) has selected Solido Variation Designer from Solido Design Automation for its STARCAD-AMS analog/mixed-signal reference Flow.