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Content tagged with Design Tools (EDA)
posted in February 2011
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Cadence extends verification IP catalog
News & Analysis  
2/28/2011   Post a comment
Cadence Design Systems Inc. announced it has opened and extended its portfolio of verification IP and memory models to support silicon to system development.
Optimal team sizes for chip projects
Blog  
2/28/2011   Post a comment
Chip design projects demand a threshold number of engineers to meet schedule targets, yet, there's a point at which adding resources yields little, if any, additional development throughput.
Evolution of manufacturing closure for advanced nodes (Part 2)
Design How-To  
2/28/2011   Post a comment
Starting at the 40/45nm design node, DRC/DFM closure emerged as a significant new challenge to IC designers. No longer could manufacturing concerns be effectively handled with the traditional design-then-verify flow. This trend is expected to continue and worsen at the 32nm and 22nm nodes, where manufacturing closure may become a serious bottleneck in design schedules.
Carbon TLM-2.0 for AMBA protocol solution
Product News  
2/25/2011   Post a comment
Carbon Design Systems Inc. has released a solution for AMBA TLM-2.0 modeling that enables virtual mode reuse in any SystemC environment.
Report from EDSFair 2011
Blog  
2/25/2011   Post a comment
At this year's ESDFair, EVE SA (Palaiseau, France) conducted a survey to determine chip design and verification trends in Japan. Check out what attendees told EVE's booth staff!
Mentor beats estimates, eyes $1 billion mark
News & Analysis  
2/24/2011   5 comments
EDA vendors Mentor Graphics and Magma Design Automation reported quarterly results that beat consensus analysts' expectations, with Mentor posting record annual revenue and saying it expects to become a $1 billion company in the current fiscal year.
DVCon is next week: UVM, recruiting, and more
Blog  
2/24/2011   Post a comment
Learn about UVM and other advancements in modern design and verification at next week's DVCon.
Plan strategies for adopting Model-Based Design for embedded applications: Part 1—Challenges and impact
Design How-To  
2/24/2011   11 comments
When transitioning to Model-Based Design for embedded systems development, it is essential to consider an overall plan spanning people, development processes, and tools.
Mentor claims comprehensive support for UVM 1.0
Product News  
2/23/2011   Post a comment
Mentor Graphics Corp. announced its comprehensive support for Accellera's Universal Verification Methodology (UVM) across a host of products including Questa advanced functional verification platform, the Questa MVC Verification IP library, the Veloce emulation platform and the Certe Testbench Studio tool.
Key factors for success in dealing with Asian fabs
Design How-To  
2/22/2011   6 comments
This article is about managing relationships with Asian semiconductor foundries through the understating of the socio-business-cultural (SBC) environment. Since Taiwan, China, Singapore, South Korea and Malaysia host the major foundries, this article gives a good insight into the factors important for fabless/fablite companies to be successful.
Do we need a new FPGA structure for prototyping?
Blog  
2/22/2011   2 comments
I have been talking to a lot of people recently about the subject of prototyping. Not only do I believe that it is one of the most important applications related to the success of ESL, but...
Check out the new HDR video camera dev kit and reference design from Lattice
Product News  
2/22/2011   2 comments
Production-ready development it and FPGA reference design accelerate time-to-market and enable full HD HDR camera designs at lowest system cost.
Imperas supports Micrium OS running on ARM model
Product News  
2/22/2011   3 comments
High-level modeling and simulation company Imperas Ltd. has released a reference virtual platform based on the ARM Cortex-M3 processor core that runs the Micrium uC/OS II real-time operating system.
Icahn makes bid to acquire Mentor
News & Analysis  
2/22/2011   15 comments
Billionaire activist investor Carl Icahn offered to buy EDA vendor Mentor Graphics for $17 per share, or about $1.9 billion total.
ADI's SPICE simulation tool upgrade allows engineers to design larger, complex circuits
Product News  
2/22/2011   Post a comment
Analog Devices, Inc., (ADI) has collaborated with National Instruments (NI) on a new release of NI's Multisim component evaluation tool with added features and functionality to provide engineers with an easy-to-use environment for the simulation of linear circuits using ADI components.
What's the best way to backup / secure the data on my computer?
Blog  
2/22/2011   13 comments
Around the middle of last week my computer crashed and burned (see The white screen of death). Fortunately, I managed to save my data, but it was a close call and it's set me to thinking...
Magillem, CEA to develop unified HW/SW design PF for complex SoCs
News & Analysis  
2/21/2011   Post a comment
Paris-based Magillem Design Services announced it has concluded a multi-year collaboration agreement with the French Atomic Energy Agency (CEA) to develop unified hardware/software design tools for complex SoCs.
Evolution of manufacturing closure for advanced nodes (Part 1)
Design How-To  
2/21/2011   Post a comment
Manufacturing closure has become a key design challenge at smaller technology nodes such as 32 and 22nm. Starting at 45/40nm, the increasing complexity of design rule checks and design-for-manufacturing rules began to stress traditional physical design flows. This trend is expected to continue and worsen at the 32/22 nm nodes, where manufacturing closure may become a serious bottleneck in design schedules.
Let go of my Legos
Blog  
2/18/2011   12 comments
Bill Neifert, Carbon's CTO, compares the design of today's SoCs with Lego bricks and outlines the analogies between the two seemingly disparate markets, from product strategy and development, product packaging and marketing to business models.
Our friends at GateRocket need your vote
Blog  
2/17/2011   6 comments
I just heard from the folks at GateRocket that they are a finalist in the EDN Innovation awards for their FPGA debug technology, but they need our help to win.
Free whitepaper - An easier way to rad-tolerant FPGA design
Blog  
2/17/2011   1 comment
I just heard from the folks at Mentor about a free whitepaper that describes how you can create rad-tolerant FPGA designs.
DATE 2011 is on track
News & Analysis  
2/16/2011   Post a comment
DATE (Design, Automation & Test in Europe) 2011 is just around the corner, and due to the high demand, an additional exhibition space has been created for more than seventy exhibitors.
Substrate scalable design tool speeds-up product development
Product News  
2/16/2011   Post a comment
Modelithics develops model of AVX's surface mount capacitor to enhance product development.
EDA focus shifts to system level design
Design How-To  
2/16/2011   Post a comment
Companies designing complex electronics always face numerous challenges, which keep evolving, because each problem solved enables new advances that in turn lead to new challenges. The year ahead will see increased system engineering content in chip- and board-level designs.
The white screen of death...
Blog  
2/16/2011   27 comments
I am not a happy person at the moment. The radiance of my smile is no longer lighting the world around me because earlier today, with no warning whatsoever, my computer gave up the ghost...
Creating the F18A – An FPGA-based TMS9918A VDP
Design How-To  
2/16/2011   14 comments
How an FPGA-newbie reproduced the TMS9918A Video Display Processor (VDP) on an FPGA so he could get VGA output from his antique TI-99/4A Home Computer.
Ease production at 65nm with DFM
Design How-To  
2/16/2011   Post a comment
The challenges of production at advanced process geometries are well-known. In anticipation of reaching today's leading-edge process nodes, EDA companies and chip foundries have been developing and perfecting DFM technology to address users' critical needs. However, many designers viewed these DFM tools with skepticism as they continued to get products to market without them.
New development kit for Tabula’s ABAX 3D FPGAs
Product News  
2/15/2011   7 comments
Comprehensive development kit delivers versatile platform for building next-generation applications with ABAX 3D Programmable Logic Devices (3PLDs) [which I think of as 3D FPGAs].
Tabula releases Stylus design software for ABAX 3D FPGAs
Product News  
2/15/2011   4 comments
Cloud-based Stylus design software delivers Spacetime’s 3D Architecture breakthrough price/performance advantages to ASIC and FPGA designers.
CoFluent joins Cadence's EDA360 System Realization Alliance
News & Analysis  
2/14/2011   Post a comment
French Electronic System Level (ESL) company CoFluent Design announced it has joined Cadence Design Systems' EDA 360 System Realization Alliance supporting the Cadence ecosystem.
MediaTek deploys Mentor's Calibre PERC
News & Analysis  
2/14/2011   Post a comment
MediaTek Inc. announced it has licensed Calibre Programmable Electrical Rule Checker (PERC), Mentor Graphics' DFM solution designed to address advanced circuit verification to ensure optimal design yield and improve reliability.
Lattice to demo new products and technologies at Embedded World
News & Analysis  
2/14/2011   2 comments
At the forthcoming Embedded World 2011 conference Lattice Semiconductor will have exhibits, displays, and demonstrations of programmable embedded design solutions that reduce costs, power, and design time.
EDA expert joins Oasys' board
News & Analysis  
2/14/2011   Post a comment
EDA startup Oasys Design Systems Inc. announced it has named Gary Meyers, an experienced EDA and semiconductor executive, to its board of directors.
I want my own Jet Pack!!!
Blog  
2/12/2011   9 comments
I know that the use of three exclamation marks (as in the title to this blog) is the sign of a deranged mind ... but I don’t care ... I want my own personal Jet Pack!!!
Tensilica to dominate LTE Advanced with ConnX BBE64-128 DSP IP core
Product News  
2/12/2011   3 comments
The new ConnX BBE64-128 DSP can perform at 128 GigaMACs per cycle for maximum throughput and minimum energy for functions used extensively in LTE Advanced software.
Insight EDA rolls ERC Analyzer Version 4.0
Product News  
2/11/2011   Post a comment
Insight EDA (Redwood City, Calif.) has released Version 4.0 of its Electrical Rule Checking (ERC) Analyzer. Aimed at mixed signal and mixed power designs, it will easily detect deeply buried domain crossing issues and help users avoid costly problems with silicon.
Synopsys adds features to DesignWare Universal DDR memory controller
Product News  
2/11/2011   1 comment
Synopsys Inc. has enhanced the architecture of its DesignWare Universal DDR Memory Controller to accelerate the access to off-chip DRAM and deliver higher throughput for SoC designs.
Standard design constraints: The next productivity boost for custom design
Blog  
2/11/2011   6 comments
Manual design methodologies are no longer sufficient for custom designs as they begin to target 45nm-and-below process methodologies. Mark Waller, VP Engineering at Pulsic, Ltd., urges the custom-design community to work together and deliver a design constraints standard that will enable all custom design teams to maximize productivity gains.
Does EMC stand for exasperating, magic, or confusing?—Part 1
Design How-To  
2/10/2011   10 comments
While it is merely a nuisance to experience radio interference, it is definitely a serious matter if an ABS, stability control, or airbag suffers a malfunction because a vehicle passes a TV tower too closely. Thus, mastering EMC is a basic requirement for automotive electronics designers. Part one of this article explains basic strategies and provides useful hints.
Synopsys, Varian to develop TCAD models for logic, memory devices
News & Analysis  
2/10/2011   Post a comment
Synopsys Inc. and Varian Semiconductor Equipment Associates Inc. have joined forces to develop Technology CAD (TCAD) models that address cryogenic ion implantation for leakage reduction of leading-edge logic and memory devices.
Analog Bits claims industry's lowest power 40-nm high bandwidth SerDes
Product News  
2/10/2011   1 comment
Analog Bits, the integrated clocking and interface IP specialist, is releasing what the company claims is the industry's lowest power 40 nm, high-speed Serializer/Deserializer IP. The macro is programmable to support multiple protocols and small enough to be used in embedded SoCs.
MunEDA joins SI2 Initiative
News & Analysis  
2/10/2011   Post a comment
MunEDA GmbH (Munich, Germany) announced it has joined the Silicon Integration Initiative (Si2) and the Si2's Open Process Design Kit Coalition (OPDKC).
Teaching an old dog (me) new tricks
Blog  
2/10/2011   24 comments
Have you seen those things called ‘The Great Courses’? These are college-level courses that are available on DVD for you to study from the comfort of your sofa. I just ordered three...
Automatic shape-based routing to achieve parasitic constraint closure in custom design
Design How-To  
2/9/2011   Post a comment
This paper details the increasing problem of achieving parasitic-constraint closure during interconnect routing and how a shape-based routing methodology can help to solve these problems automatically while completing the routing of the design.
Another activist investor targets Mentor
News & Analysis  
2/8/2011   5 comments
Activist hedge fund Casablanca Capital has written a letter to Mentor Graphics' board of directors saying it will nominate a new slate of directors to the company's board after Mentor announced that it would hold its annual shareholder meeting on May 12, more than a month earlier than it was held in 2010.
So, what would you do?
Blog  
2/8/2011   1 comment
Speaking of human mirrors, did you see…? And what about...? And you must have seen…! So what do you think you would do if you were ever faced with a situation like...?
AWR releases impedance matching module
Product News  
2/8/2011   Post a comment
AWR announces iMatch, an automated impedance matching module
Altera FPGA I/F targets serial, high-density Bandwidth Engine device from MoSys
Product News  
2/8/2011   3 comments
Support for MoSys GigaChip interface in Stratix IV GT FPGA provides developers of 100G wireline applications a proven high-performance serial memory solution.
Europractice adopts vfAnalyst for cloud EDA
News & Analysis  
2/8/2011   Post a comment
Vector Fabrics has announced that its internet-based vfAnalyst software-parallelizing tool is now available to researchers across Europe on a contract with the Europractice EDA software service.
STARC adopts Solido variability tool
News & Analysis  
2/8/2011   1 comment
The Semiconductor Technology Academic Research Center (STARC) has selected Solido Variation Designer from Solido Design Automation for its STARCAD-AMS analog/mixed-signal reference Flow.
Page 1 / 2   >   >>


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