U.S.-based Cradle hopes India's software will reshape MPU business News & Analysis 3/30/2001 Post a comment DELHI, India--Silicon Valley startup Cradle Technologies Inc. today (March 30) launched a software initiative in India to build development support for its Universal Micro System (UMS) platform and plant the seeds for a new crop of "chipless chip" companies that could redefine the microprocessor business.
Innoveda to phase out PowerLogic tool News & Analysis 3/26/2001 Post a comment EDA tools company Innoveda is to phase out PowerLogic as a stand-alone schematic capture package as it deals with a couple of product overlaps in its portfolio, following the PADS Software purchase last year.
NEC, Tera forge ASIC library deal to accelerate sub-micron chip designs News & Analysis 3/22/2001 Post a comment SANTA CLARA, Calif. -- In a move to accelerate sub-micron chip designs, NEC Electronics Inc. announced that it will offer Tera Systems Inc.'s timing and layout EDA tools in its ASIC libraries.
Under the plan, NEC will offer Tera's TeraGate libraries in its 0.25- and 0.18-micron process. TeraGate enables the use of Tera's register-transfer-level (RTL) design planning tool. Dubbed TeraForm, the tool enables designers to identify and correct RTL code that will cause downstream gate-level timing an
ARM tacks on switch to boost on-chip bus bandwidth News & Analysis 3/21/2001 Post a comment ARM has developed an addon to its current AMBA hardware bus (AHB) specification that lets chip designers multiply the total bandwidth available in a system without changing the bus interface on existing intellectual property (IP) cores.
Magma rewrites noise analysis tool News & Analysis 3/19/2001 Post a comment Magma Design Automation is set to release a follow-up to the GateScope noise analysis tool it acquired when it bought Moscape and has stopped pushing the current version.
To Chip Designers, Test is a Four-Letter Word News & Analysis 3/19/2001 Post a comment You don't have to like implementing design-for-test in your chips, but you have to do it. Help is on the way through cooperative efforts between vendors that develop chip DFT software and companies that manufacture chip test equipment.
IP search tool pulls in data from web databases News & Analysis 3/16/2001 Post a comment A collaborative effort between researchers at Stanford University and the University of Bologna is producing a new Java-based tool that promises to allow users on the web to more easily query IP repositories and commercial databases to find the core best suited for a given design project.
SystemC attacked over licence terms at DATE panel News & Analysis 3/16/2001 Post a comment Wally Rhines, chairman and CEO of Mentor Graphics attacked the Open SystemC Initiative (OSCI) at a chief executives' panel debate held 15 March at the Design Automation and Test Europe (DATE) conference in Munich, but said Mentor would embrace the group if key changes were made in the bylaws.
NeoLinear hands tool sales over to Cadence News & Analysis 3/15/2001 Post a comment Cadence has picked up the exclusive rights to sell NeoLinear's analogue design tools, kicking off with a library cell-design package. The deal comes at the same time that Cadence has inked deals with PDF Solutions and Silicon Metrics to integrate support for process simulation and library characterisation into its tools.
EDA vendors could lose edge to chip makers, keynoter warns News & Analysis 3/14/2001 Post a comment EDA vendors must work more closely with large semiconductor suppliers and customers to close growing design gaps or risk losing that chore to the semiconductor industry, according to Peter Bauer, executive vice president of Infineon Technologies AG, in a keynote address delivered Wednesday (March 13) to the Design Automation and Test in Europe conference.
Analogue converters put focus on SoC test costs News & Analysis 3/14/2001 Post a comment Logicvision is working on a project that will bring on-chip test to mixed-signal designs that use analogue-to-digital converters (ADCs) in an attempt to stop the rise in test costs, particularly for complex system-on-chip (SoC) designs. At the same time, Agilent Technologies and Synopsys have cut a deal in which the two companies will try to optimise test software for SoC production.
ST tries new flow with Magma tool News & Analysis 3/14/2001 Post a comment STMicroelectronics is to use Magma Design Automation's BlastFusion in a project based at Agrate, Italy to develop a new flow for 0.18um designs and below. The announcement is part of the latest salvo over tapeouts from integrated synthesis and place-and-route flows.
Cadence, PDF inks deal to develop yield-analysis software tools for chip makers News & Analysis 3/13/2001 Post a comment SAN JOSE -- Cadence Design Systems Inc. and PDF Solutions Inc. here today (March 13) announced plans to co-develop a line of yield-analysis software tools for making analog and mixed-signal chips.
The software tools will be designed to improve the performances and yields of chips from both fabless chip makers and integrated device manufacturers (IDMs), according to the companies.
Adaptive Silicon claims to cut cost of embedded programmable logic in SoC designs News & Analysis 3/12/2001 Post a comment MUNICH -- What's best--embedding chunks of programmable logic in large system-on-chip (SoC) designs, or integrating standard functions in large programmable logic devices? Privately-held Adaptive Silicon Inc., founded by former managers from National Semiconductor Corp., believes embedded programmable logic in multi-million-gate ASICs and standard ICs is the best way to go.
TSMC and Cadence team up on communications chips News & Analysis 3/8/2001 Post a comment As part of an ongoing effort to increase its communications-chip business, Taiwan Semiconductor Manufacturing Co. Ltd. has aligned with the largest EDA vendor to help time-pressured communications customers get products to market more quickly.
ARC goes for naming strategy News & Analysis 3/7/2001 Post a comment ARC International, the microprocessor cores intellectual property company, admits that naming major customers has become a vital part of its strategy to bolster it against the current industry downturn.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments