"Better Design Productivity" Pervasive at Board-Design Show News & Analysis 3/26/2002 Post a comment The recent Silicon-Valley based PCB Design conference and exhibition concentrated on new tools and tool enhancements to help board engineers and designers improve existing design methodologies. TechOnLine's Jim Lipman discusses how the show's exhibitors concentrated on new tool bundles, Web-based collaborative design, and enhanced design functionality for mainstream board designers.
Specialization seen hindering SoC progress News & Analysis 3/6/2002 Post a comment The system-on-chip era is widening the gap between designers and manufacturers who have been forced by industry specialization into speaking different languages, a trend that does not bode well for future SoC projects, according to Taylor Scanlon, president and chief executive officer of Virtual Silicon Technology Inc. (Sunnyvale, Calif.), in a keynote at the Design Automation and Test in Europe conference.
Phase-shift masks to move up the stack News & Analysis 3/6/2002 Post a comment Numerical Technologies is trying to take its phase-shift mask technology out of just making shorter gates and into the interconnect layers of chips as the chipmakers try to push 193nm equipment deeper into the sub-100nm zone.
VSIA ready to move to next stage on signal integrity News & Analysis 3/6/2002 Post a comment The Virtual Socket Interface Alliance (VSIA) says it is close to completing a standard that will let intellectual property (IP) core providers specify how their offerings will perform in the increasingly unpredictable conditions of chips built using deep submicron processes.
Transeda adds properties to gauge design-check coverage News & Analysis 3/5/2002 Post a comment UK-based design tools company Transeda has joined the move to use formal specification to drive hardware simulation. The company says it sees tests based on formally specified properties as being the key to reusing verification code and to build up both its own and a third-party library of test code.
Design-check languages move onto hardware News & Analysis 3/4/2002 Post a comment Developers of design verification tools are putting code from higher-level languages directly on to hardware to speed up the design-checking process. The languages involved include C and dedicated testbench languages such as 'e' and Vera.
Flomerics down but in the black News & Analysis 3/4/2002 Post a comment Flomerics, the UK supplier of thermal and EMC simulation software to the electronics industry, reported a 9% rise in turnover to £12.9m for the full year to the end of December.
Tool revision floorplans using power News & Analysis 3/4/2002 Post a comment Germany's Offis Systems and Consulting (OSC) is readying its Orinoco power analysis tool for a commercial release, having added the ability to perform power-optimised floorplanning.
Value of Verification Fits Survival Profile News & Analysis 3/1/2002 Post a comment Achieving functional closure, or ensuring that designs meet their functional specification from RTL to final layout, continues to be one of the greatest challenges for today's ASIC and system-on-chip design teams.
FPGA Is as Good as its Embedded Plan News & Analysis 3/1/2002 Post a comment The inclusion of embedded processors in programmable-logic devices has enabled system-on-chip developers to benefit from the traditional time-to-market advantages of programmable logic.
Embedded EE Array Grows a BISTy Core News & Analysis 3/1/2002 Post a comment MI Semiconductor has developed for its smaller-geometry processes several types of nonvolatile memory macrocells, including a nonvolatile latch for situations that require a very small amount of nonvolatile memory;