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Content tagged with Design Tools (EDA)
posted in March 2002
New Devices, Design Tools Fuel Programmable Logic Resurgence
Design How-To  
3/28/2002   Post a comment
Jim Lipman, TechOnLine's Content Director, discusses a continued interest by FPGA/CPLD vendors in configurable SoC chips along with reasons why programmable-logic design is becoming more "ASIC-like".
Mentor says it now holds 85.6% of IKOS shares in takeover bid
News & Analysis  
3/27/2002   Post a comment
WILSONVILLE, Ore.--Mentor Graphics Corp. here today announced it has purchased 7.8 million shares of IKOS Systems Inc. in its bid to buy the San Jose-based supplier of design verification systems.
PDF offers yield-analysis package to fabless chip houses for foundry processes
News & Analysis  
3/26/2002   Post a comment
SAN JOSE--PDF Solutions Inc. here announced a new yield-improvement technology package for fabless semiconductor companies to help them quickly make design changes in products without impacting the supply of devices coming from silicon foundries.
"Better Design Productivity" Pervasive at Board-Design Show
News & Analysis  
3/26/2002   Post a comment
The recent Silicon-Valley based PCB Design conference and exhibition concentrated on new tools and tool enhancements to help board engineers and designers improve existing design methodologies. TechOnLine's Jim Lipman discusses how the show's exhibitors concentrated on new tool bundles, Web-based collaborative design, and enhanced design functionality for mainstream board designers.
Mentor eyes hardware emulation for mainstream prototyping
News & Analysis  
3/19/2002   Post a comment
CEO Wally Rhines outlines new strategy as company closes on Ikos takeover.
Cadence will buy Plato Design to enhance SoC routing technology
News & Analysis  
3/13/2002   Post a comment
SAN JOSE -- Cadence Design Systems Inc. here today announced an agreement to acquire privately-held Plato Design Systems of San Jose in a move to enhance its system-on-chip routing technology. Terms of the acquisition were not released.
Specialization seen hindering SoC progress
News & Analysis  
3/6/2002   Post a comment
The system-on-chip era is widening the gap between designers and manufacturers who have been forced by industry specialization into speaking different languages, a trend that does not bode well for future SoC projects, according to Taylor Scanlon, president and chief executive officer of Virtual Silicon Technology Inc. (Sunnyvale, Calif.), in a keynote at the Design Automation and Test in Europe conference.
Phase-shift masks to move up the stack
News & Analysis  
3/6/2002   Post a comment
Numerical Technologies is trying to take its phase-shift mask technology out of just making shorter gates and into the interconnect layers of chips as the chipmakers try to push 193nm equipment deeper into the sub-100nm zone.
VSIA ready to move to next stage on signal integrity
News & Analysis  
3/6/2002   Post a comment
The Virtual Socket Interface Alliance (VSIA) says it is close to completing a standard that will let intellectual property (IP) core providers specify how their offerings will perform in the increasingly unpredictable conditions of chips built using deep submicron processes.
Startup crafts tool to create custom processors
News & Analysis  
3/6/2002   Post a comment
A US-based startup has taken technology developed at the University of Aachen that can be used to build custom embedded processors automatically from a high-level description.
Transeda adds properties to gauge design-check coverage
News & Analysis  
3/5/2002   Post a comment
UK-based design tools company Transeda has joined the move to use formal specification to drive hardware simulation. The company says it sees tests based on formally specified properties as being the key to reusing verification code and to build up both its own and a third-party library of test code.
Design, Automation and Test in Europe Conference news
News & Analysis  
3/4/2002   Post a comment
EETimes reports from the Design, Automation and Test in Europe conference held in Paris 4-8 March 2002.
Design-check languages move onto hardware
News & Analysis  
3/4/2002   Post a comment
Developers of design verification tools are putting code from higher-level languages directly on to hardware to speed up the design-checking process. The languages involved include C and dedicated testbench languages such as 'e' and Vera.
Memory scheduler to keep accesses on deadline
News & Analysis  
3/4/2002   Post a comment
Sonics, a US-based specialist in on-chip networks, has devised what it calls a memory scheduler to co-ordinate accesses between multiple processors on a chip.
Flomerics down but in the black
News & Analysis  
3/4/2002   Post a comment
Flomerics, the UK supplier of thermal and EMC simulation software to the electronics industry, reported a 9% rise in turnover to £12.9m for the full year to the end of December.
Tool revision floorplans using power
News & Analysis  
3/4/2002   Post a comment
Germany's Offis Systems and Consulting (OSC) is readying its Orinoco power analysis tool for a commercial release, having added the ability to perform power-optimised floorplanning.
Value of Verification Fits Survival Profile
News & Analysis  
3/1/2002   Post a comment
Achieving functional closure, or ensuring that designs meet their functional specification from RTL to final layout, continues to be one of the greatest challenges for today's ASIC and system-on-chip design teams.
Security Chip Design Speeds on to Silicon
News & Analysis  
3/1/2002   1 comment
When we founded our company in September 2000, existing ASIC solutions were not keeping pace with the Internet infrastructure buildout, causing a performance bottleneck.
FPGA Is as Good as its Embedded Plan
News & Analysis  
3/1/2002   Post a comment
The inclusion of embedded processors in programmable-logic devices has enabled system-on-chip developers to benefit from the traditional time-to-market advantages of programmable logic.
Embedded EE Array Grows a BISTy Core
News & Analysis  
3/1/2002   Post a comment
MI Semiconductor has developed for its smaller-geometry processes several types of nonvolatile memory macrocells, including a nonvolatile latch for situations that require a very small amount of nonvolatile memory;
Processor Fits Into Pin-Limited Design
News & Analysis  
3/1/2002   Post a comment
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What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.
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