Why you need RTL virtual prototyping
News & Analysis 3/28/2003 Post a comment
Cadence Design Systems' Suk Lee traces the evolution of silicon virtual prototyping, and proposes a "continuous convergence" methodology for solving timing closure problems.
Simple techniques for making verification reusable
News & Analysis 3/21/2003 Post a comment
Peter Spyra, verification engineer at design services startup Integre Technologies, describes a number of techniques for verification reuse with Verisity's "e" language in this detailed tutorial. An accompanying article provides code examples.
Mobile generation needs FRAM
News & Analysis 3/17/2003 Post a comment
In the late 1990s, after more than a decade of ferroelectric-memory development, several companies succeeded in the high-volume production of low-density (less than 1-Mbit) ferroelectric RAM.
What designers need to know about structural test
News & Analysis 3/6/2003 Post a comment
As functional testing becomes impractical, structural IC test becomes crucial, says Credence's Marc Loranger (right). In this tutorial, he shows you why, and details the EDA software and ATE hardware that's needed to support it.
Fault coverage founders on speed
News & Analysis 3/3/2003 Post a comment
Regardless of the test methodology employed, the goal of manufacturing test is to identify, or screen out, defective devices before they are embedded into a system or shipped to the end customer.