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posted in March 2003
Why you need RTL virtual prototyping
News & Analysis  
3/28/2003   Post a comment
Cadence Design Systems' Suk Lee traces the evolution of silicon virtual prototyping, and proposes a "continuous convergence" methodology for solving timing closure problems.
Simple techniques for making verification reusable
News & Analysis  
3/21/2003   Post a comment
Peter Spyra, verification engineer at design services startup Integre Technologies, describes a number of techniques for verification reuse with Verisity's "e" language in this detailed tutorial. An accompanying article provides code examples.
Manufacturability, scalability: a critical test of SoC memories strategies
News & Analysis  
3/17/2003   Post a comment
Since no one questions the performance benefits of embedding large memory blocks in SoCs, the only major issues to address are cost, time to market and design risk.
Speed with flexible design critical to embedded DRAM for SoCs
News & Analysis  
3/17/2003   Post a comment
The incorporation of embedded dynamic random-access memory (DRAM) in a system-on-chip (SoC) environment presents some unique challenges.
Nonvolatile memories for 90nm SoC and beyond
News & Analysis  
3/17/2003   Post a comment
In many SoC applications, it is desirable to store code and data in a non-volatile memory to maintain the state of the system even in the power-off state.
Merged-logic-type embedded DRAM suits high-performance SoCs
News & Analysis  
3/17/2003   Post a comment
To push access times toward those of SRAM while achieving much higher densities, embedded DRAM needs a structure that differs from both commodity DRAM and conventional embedded DRAM.
Mobile generation needs FRAM
News & Analysis  
3/17/2003   Post a comment
In the late 1990s, after more than a decade of ferroelectric-memory development, several companies succeeded in the high-volume production of low-density (less than 1-Mbit) ferroelectric RAM.
Combined coverage methodology speeds verification
News & Analysis  
3/13/2003   Post a comment
If you really want to speed verification, you need a methodology that combines functional, code, and assertion coverage. In this tutorial article, Verisity engineer Sharon Rosenberg shows you how to do that.
What designers need to know about structural test
News & Analysis  
3/6/2003   Post a comment
As functional testing becomes impractical, structural IC test becomes crucial, says Credence's Marc Loranger (right). In this tutorial, he shows you why, and details the EDA software and ATE hardware that's needed to support it.
Shifting from functional to structured techniques improves test quality
News & Analysis  
3/3/2003   Post a comment
It is becoming clear that functional testing of integrated circuits, the most widely used and oldest method in the semiconductor industry has reached the limits of its effectiveness.
Pre-configured DFT structures can simplify ASIC design, verification
News & Analysis  
3/3/2003   Post a comment
The integration of test capabilities into the underlying structure of an ASIC eliminates the extra design-for-test (DFT) steps that complicate conventional front- and back-end design flows.
Moving DFT to RTL overcomes test vector issues
News & Analysis  
3/3/2003   Post a comment
In the IC design flow, design-for-test is often an afterthought.
Linking synthesis with DFT key for network switch ICs
News & Analysis  
3/3/2003   Post a comment
As the challenges of network execution time reach new heights, the question of integrating synthesis and design-for-test (DFT) in the fabrication of high density networking devices merits reassessment.
Interoperability testing is critical for broadband deployments
News & Analysis  
3/3/2003   Post a comment
When end users employ broadband, they expect to have seamless and reliable accessibility to any application or service, no matter the system or software provider.
EDA/Design for Test
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3/3/2003   Post a comment
Fault coverage founders on speed
News & Analysis  
3/3/2003   Post a comment
Regardless of the test methodology employed, the goal of manufacturing test is to identify, or screen out, defective devices before they are embedded into a system or shipped to the end customer.
DFT: A systems technology for system chips
News & Analysis  
3/3/2003   Post a comment
Recently, DFT elements have begun to show up in more and more large complex SoC devices.
Creating Value Through Test
News & Analysis  
3/3/2003   Post a comment
Bandwidth match avoids I/O snarl
News & Analysis  
3/3/2003   Post a comment
Scan is the most general and pervasive digital structural-test technique, one that has been a standard in the industry for years.
Analog circuits need more than just DFT methods
News & Analysis  
3/3/2003   Post a comment
Digital design is, of necessity, performed at a very high level of abstraction.


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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