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posted in March 2004
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Sequence claims key optimization patents
News & Analysis  
3/30/2004   Post a comment
Sequence Design has announced four new patents that cover key analysis and optimization technology, according to the company. The patents cover clock tree insertion, circuit optimization, zero-skew buffer insertion, and match delay buffer insertion.
Zuken gives prototyping tool a tweak
News & Analysis  
3/29/2004   Post a comment
Enhancements to the latest version of Zuken Ltd.'s pc-board virtual prototyping tool, Hot-Stage 4.2, allow verification of complete electronic systems.
SystemC tool adds top-down design
News & Analysis  
3/29/2004   Post a comment
System-level tool vendor CoWare Inc. has added graphics-based front-end design software and other features to the System Designer tool of ConvergenSC, its family of SystemC-based system-on-chip design and verification products.
Chip-level specification needs a new emphasis
News & Analysis  
3/27/2004   Post a comment
Chip-level specifications shouldn't rely on spreadsheets. What's needed are estimation and analysis tools that can help make specifications accurate and correct, says Giga Scale IC's George Janac.
A look inside electronic system level (ESL) design
Design How-To  
3/27/2004   Post a comment
You've heard the buzzword, but what's ESL really all about? Vincent Perrier (right), director of CoFluent Design, explains ESL design stages, styles, and levels of abstraction, and calls for a new capability called a System Design Environment (SDE).
Synopsys CEO defends MoSys acquisition
News & Analysis  
3/26/2004   Post a comment
Responding to user questions on a variety of topics, Aart de Geus, Synopsys CEO, defended his company's proposed acquisition of MoSys in a new E-Mail Synopsys User's Group (ESNUG) mailing. De Geus was responding to questions asked at a recent EDA CEO panel that he was unable to attend.
Program Your Way To SoC Success With FPGAs
Design How-To  
3/26/2004   Post a comment
With silicon rapidly evolving from single-function devices to more intricate SoCs that pack myriad functions on just one die, designers are facing unprecedented levels of complexity. Improvements in process technology continue to push the theoretical limits of wiring to create crosstalk bedlam. The need to integrate existing or third-party IP offer unusual challenges to teams accustomed to building chips from scratch. And, design tools and methods often solve yesterday's problems better than cur
HDL generation language adds open-source license
News & Analysis  
3/25/2004   Post a comment
Confluence, a declarative programming language that generates RTL code, C language models, and formal verification models, is now available under the GNU General Public License. The new Confluence 0.9 release also adds executable simulation models, automatic HTML documentation, and a new standard library.
LTRIM solution streamlines power management needs for Bluetooth/Wi-Fi Devices
Product News  
3/25/2004   Post a comment
LTRIM Technologies, a provider of CMOS analog virtual components and Laser fine tuning technologies, unveiled its new PowerTrimPaK integrated power management solution for Bluetooth and Wi-Fi SoCs. This marks the first step in the company's plan to provide SoC developers with a comprehensive portfolio of high-performance, laser-trimmable analog IP blocks.
Multiple PLL macros meets low-latency needs of Wireless Network Processor
Product News  
3/25/2004   Post a comment
Multiple True Circuits PLL hard macros were used in a manufacturer's wireless network processor using TSMC's 130nm process technology.
PDK 'checklist' aids analog, RF designers
News & Analysis  
3/24/2004   Post a comment
Seeking to make life easier for analog, mixed-signal and RF designers, the Fabless Semiconductor Association (FSA) has approved a standardized checklist that describes the content of process design kits (PDKs). The effort complements a new Accellera initiative to standardize data representations within PDKs.
Panelists laud 'Nordstrom' approach to IP quality
News & Analysis  
3/24/2004   Post a comment
Which is the better model for ensuring silicon intellectual property (IP) quality — an off-the-shelf approach like K-Mart, or one that involves a more intimate customer/provider partnership, like Nordstrom? In a panel at the International Symposium on the Quality of Electronic Design (ISQED) here March 23, sentiment clearly rested with the Nordstrom approach.
PDK 'checklist' aids analog, RF designers
News & Analysis  
3/23/2004   Post a comment
Seeking to make life easier for analog, mixed-signal and RF designers, the Fabless Semiconductor Association (FSA) has approved a standardized checklist that describes the content of process design kits (PDKs). The effort complements a new Accellera initiative to standardize data representations within PDKs.
Panelists cite shortcomings of process design kits
News & Analysis  
3/23/2004   Post a comment
The process design kits (PDKs) issued by foundries to chip designers are difficult to keep current, and may place too much reliance on design rules, according to panelists at the International Symposium on Quality Electronic Design (ISQED) here March 22.
MIT technology fuels startup's synthesis tool
News & Analysis  
3/22/2004   Post a comment
EDA startup Bluespec Inc. this week will announce an exclusive license from the Massachusetts Institute of Technology (MIT) for synthesis technology based on term rewriting systems (TRS). Its creator, Prof. Arvind (right), says TRS allows a new approach to high-level synthesis.
Spec raises bar for IP and SoC verification
News & Analysis  
3/19/2004   Post a comment
The Virtual Socket Interface Alliance (VSIA) has set forth a specification describing "best practices" for silicon IP verification. The VSIA's Thomas Anderson explains why.
A new vision of 'scalable' verification
News & Analysis  
3/19/2004   Post a comment
Concerned about functional verification? Brian Bailey (right), Mentor Graphics' chief technologist, shows how you can reduce the verification gap with a "scalable" solution that includes assertion-based testbenches and improved debugging.
Verilog reader/writer boosts OpenAccess reach
News & Analysis  
3/18/2004   Post a comment
Plugging a major gap that has made it difficult for chip designers and EDA vendors to embrace the OpenAccess database, Hewlett-Packard and Cadence Design Systems have donated a Verilog reader/writer to the OpenAccess Coalition.
System-on-Chip Road Map
News & Analysis  
3/18/2004   Post a comment
'Live' toolkit does it all
News & Analysis  
3/17/2004   Post a comment
You can design an FPGA, program its processor core, and design the board it sits on with Altium's "LiveDesign-enabled" product line. Here's a closer look.
It Takes tools to Raise a Programmable Mixed Signal SOC
News & Analysis  
3/17/2004   Post a comment
Modern systems-on-chip are very complex devices that place large demands on the skills of the developer.
Effective System Verification with a Scalable Verification Methodology
News & Analysis  
3/17/2004   Post a comment
Functional verification is a major challenge for electronic designers today.
Mixed-Signal Verification Methodology Using Nanosim Integration with VCS
News & Analysis  
3/17/2004   Post a comment
With gate counts and system complexity growing exponentially, new submicron technologies pose many challenges in both the design and verification domains.
Mastering Mixed-Signal Verification
News & Analysis  
3/17/2004   Post a comment
The verification of mixed-signal designs shares all the problems associated with verifying digital designs--for example, detecting complex corner case bugs.
For SoC, It's the Whole - Not the Parts
News & Analysis  
3/17/2004   Post a comment
Remember the Hubble telescope? All the components were built and tested in isolation; they met spec. Only after these parts were first brought together, in space, was it discovered that the system failed to perform as expected. Space is a very costly place to repair a telescope.
Solutions for Managing Complex SoC Design
News & Analysis  
3/17/2004   Post a comment
Designers of silicon systems-on-a-chip are facing many problems, not least the sheer physical challenge of putting up to 100 million transistors on one IC.
System-on-Chip Road Map
News & Analysis  
3/17/2004   Post a comment
Tackling multiple clocks in SoCs
News & Analysis  
3/17/2004   Post a comment
Multiple clocks are inevitable in today's designs. Systems-on-chip (SoCs) have grown significantly in complexity, as well as in the variety of intellectual-property (IP) blocks that can be integrated.
System-circuit view of mixed-signal design
News & Analysis  
3/17/2004   Post a comment
Figuring out how to integrate more and more analog and digital blocks on a single chip has become a difficult task.
Hearing-aid SoC: Tiny gear, big challenges
News & Analysis  
3/17/2004   Post a comment
Few products present more stringent power dissipation, analog functionality and area requirements than modern hearing aids.
FPGAs step up to SoC challenge
News & Analysis  
3/17/2004   Post a comment
Now that FPGAs are changing the system-on-chip road map, SoCs are no longer the sole purview of ASICs.
The Hard Truth about System-on-Chip Designs
News & Analysis  
3/17/2004   Post a comment
The trend toward integration of analog and digital functions in the wireless infrastructure market has intensified over the last five years, as integration is viewed as the best way to reduce overall system cost and size.
The Tao of analog/mixed-signal and digital integration
News & Analysis  
3/17/2004   Post a comment
Perhaps the 2003 edition of the International Technology Roadmap for Semiconductors (ITRS) sums up the system-on-chip design challenge well: SoC design "is characterized by heavy reuse of intellectual property (IP) to improve design productivity, and by system integration that potentially encompasses heterogeneous technologies."
Mentor's Rhines predicts PCB retooling
News & Analysis  
3/17/2004   Post a comment
The pc-board tools segment of the EDA industry is seen today as a mature, consolidated and somewhat stagnant market, but it's going to liven up soon, according to Mentor Graphics CEO Wally Rhines (right), who gave the keynote speech at the PCB Design Conference West Tuesday.
'Over the top' routing boosts PCB speeds
News & Analysis  
3/16/2004   Post a comment
A new approach to pc-board routing can boost chip-to-chip interconnect speeds to 20 Gbits/second, dramatically speeding system performance, according to Joe Fjelstad, founder of technology startup SiliconPipe. At the PCB Design Conference West here, Fjelstad described a method of routing high-speed signals off the top of chip packages.
DSP synthesis tool supports FPGAs, ASICs, and structured ASICs
Product News  
3/16/2004   Post a comment
A DSP Synthesis tool has been introduced by AccelChip Inc. to accelerate the ASIC and FPGA development process by providing automatic implementation and verification flow for DSP algorithms.
'Algorithm-to-tapeout' synthesis rolls
News & Analysis  
3/15/2004   Post a comment
Claiming to offer the first "algorithm-to-tapeout" synthesis tool, startup Synfora Inc. this week will unveil a tool that lets users design compute-intensive blocks from C-language algorithms. Pico Express works with a customizable intellectual-property (IP) block called a Pipeline of Processor Array, or PPA.
Startup looks to fill Cadence CCT vacuum
News & Analysis  
3/15/2004   Post a comment
ConnectEDA, a pc-board tools startup, aims to fill a gap left when Cadence Design Systems Inc. stopped making its CCT autorouter available for sale by competing EDA vendors in the late 1990s.
Synopsys takes another stab at FPGA synthesis
News & Analysis  
3/15/2004   Post a comment
Making its fourth run at FPGA synthesis, Synopsys Inc. has tweaked its Design Compiler ASIC synthesis tool to enable designers to use the same tools and potentially the same design flow for ASICs and FPGAs. The $19,600 add on will be announced this week.
Firmware friendly chip-level design techniques
Design How-To  
3/13/2004   Post a comment
Want that chip to go out the door? David Fechser (right), LSI Logic's "firmware friendly" engineer, returns to EEdesign with a tutorial that shows you how to design chips the firmware team can actually program. Topics include functional block control, debugging considerations, and exception handling.
Cadence Allegro platform delivers high-speed interconnect design
Product News  
3/11/2004   Post a comment
Cadence Design Systems, Inc. has released its Cadence Allegro system interconnect design platform to optimize and accelerate high-performance, high-density interconnect designs. The new platform combines best-of-breed design and analysis tools with a new co-design methodology across three design domains for the IC, package and PC-board.
User lauds unreleased Design Compiler version
News & Analysis  
3/11/2004   Post a comment
A special pre-release version of Synopsys' Design Compiler synthesis tool is demonstrating huge improvements in runtime and memory capacity, according to an engineer who reviewed the tool for the E-Mail Synopsys Users Group. Synopsys confirmed that the engineer's statements are correct.
Engineer offers free obfuscator, layout scanner
News & Analysis  
3/10/2004   Post a comment
Inspired by a user request in the E-Mail Synopsys Users Group (ESNUG), an engineer working in Singapore developed a Verilog source-code obfuscator, a GDSII layout viewer, and a layout scanner that calculates wire length. All are available for free downloading from Eng Han Lee's web site.
Mentor expands Chinese university program
News & Analysis  
3/10/2004   Post a comment
Helping train a new generation of chip and PCB designers, Mentor Graphics has announced its intent to provide EDA products, training, and support to nine top Chinese universities. Mentor announced Tuesday (March 9) that it had signed a memorandum of understanding (MOU) with the Chinese Ministry of Education to provide the support.
Timing constraints should be generated up front
News & Analysis  
3/9/2004   Post a comment
Synthesis tools spend too long trying to optimize false and multi-cycle paths. A better approach is a design methodology that automatically generates and verifies timing exceptions, says FishTail CEO Ajay Daga.
Celoxica offers FPGA evaluation boards
News & Analysis  
3/8/2004   Post a comment
Complementing its C-language FPGA design tools, Celoxica Ltd. has released two FPGA-based evaluation and prototyping boards. Aimed at image processing and data streaming applications, the boards provide a link between system-level design and physical implementation.
Page 1 / 2   >   >>


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