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Content tagged with Design Tools (EDA)
posted in March 2004
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Chip design knights ride to slay power dragon
News & Analysis  
3/8/2004   Post a comment
Chip designers are wielding new weapons in the struggle to control power leakage. Transistors with more than one threshold voltage, chips with multiple voltage "islands" and substrate-biasing techniques are among the schemes being brought to bear to quell what an IBM manager called "clearly the most pressing problem facing our industry, one that threatens our very lifeblood." David Lammers has this report.
Readers' Choice Award Winner: Agilent's FPGA logic analyzer
Product News  
3/8/2004   Post a comment
Agilent's latest high-speed logic analyzers, hosted by Windows PCs, will let you look into a design's signals with a variety of new tricks. These latest boxes leverage advanced computing and gigabit local area networking to achieve their stellar performance specs. But, there's more to it than that---especially when it comes to FPGAs. Visitors to eeProductCenter during electronicaUSA selected this as one of the significant new products.
Cadence platform models chip-to-board interconnect
News & Analysis  
3/8/2004   Post a comment
Cadence Design Systems Inc. this week will release Allegro, a platform that can model the high-speed interconnect of an entire system, from ICs through packages to pc boards.
Silicon modeling in the nanometer era
News & Analysis  
3/8/2004   Post a comment
90 and 65 nm designs pose increasing challenges: finer line widths, longer interconnect, more routing layers and more analog content. A new approach to modeling and extraction is needed.
Chip design knights ride to slay power dragon
News & Analysis  
3/8/2004   Post a comment
Chip designers are wielding new weapons in the struggle to control power leakage. Transistors with more than one threshold voltage, chips with multiple voltage "islands" and substrate-biasing techniques are among the schemes discussed at an IBM conference on energy-efficient design.
Integrated development tool brings power-management to power
Product News  
3/6/2004   Post a comment
Power-One bills its Z-Series system, built around its touted "Z-One Digital IBA" architecture, as the first truly integrated power-management-with-power-conversion development tool for board-level applications. The highly scaleable system, using in-house silicon to eliminate component incompatibility issues and to cut system development costs by 20 percent, board space by half, and component count by 90 percent, includes the company's 20-amp Z-POL DC/DC (ZY7120) point-of-load converter; a digita
Power-management designer cuts time-to-market
Product News  
3/5/2004   Post a comment
Potentia Semiconductor's PowerCenter design tool simplifies power management designs in board-mounted systems, cutting development time from weeks to hours. The hardware-with-software product includes a family of four isolated/non-isolated power subsystem controller chips and emulator hardware, glued together by point-and-click software that enables designers to quickly envision topology and configure their requirements for monitoring, sequencing, margining, and fault handling for multi-rail sys
A new approach to nanometer delay modeling
News & Analysis  
3/4/2004   Post a comment
A new delay calculation method is needed for nanometer designs, says Cadence Design Systems' Rahul Deokar (right). In this feature article, he proposes a methodology that leverages waveform-dependent effective capacitance, variable current source modeling, and nonlinear modeling of IR drop impact.
Panel debates viability of ESL tools market
News & Analysis  
3/4/2004   Post a comment
As IC designs become larger and more complex, there is a growing need for electronic system level (ESL) design tools. But according to panelists and attendees at the Design and Verification Conference (DVCon) Wednesday, March 3rd, ESL has not yet proven to be a viable business for big EDA tool vendors.
Vendors make progress on Verilog 2001 compliance
News & Analysis  
3/4/2004   Post a comment
EDA vendors have made considerable progress within the past year in complying with the Verilog 2001 standard, but there are still a few weak areas, according to Cliff Cummings (right), president of consulting firm Sunburst Design. Cummings spoke at this week's DVCon conference.
EDA CEOs field provocative questions
News & Analysis  
3/3/2004   Post a comment
In a broad-ranging panel discussion at the Design and Verification Conference (DVCon) here Tuesday (March 2), moderator John Cooley (right) asked EDA CEOs a variety of provocative questions — and received some spirited responses. Topics included structured ASICs, SystemC, SystemVerilog, synthesis, and the outsourcing of jobs to India and China.
Cadence CEO pitches 'platform' to help cut costs
News & Analysis  
3/3/2004   Post a comment
Faced with rapidly rising costs, chip design firms need to turn to "platforms" such as Cadence Design Systems' Incisive verification tool suite, said Ray Bingham (right), Cadence president and CEO, at a keynote speech at the Design and Verification Conference (DVCon) Tuesday (March 2).
Virtuoso unifies mixed-signal, analog flows
News & Analysis  
3/2/2004   Post a comment
Cadence Design Systems Inc. will announce this week that its Virtuoso Custom Design Platform is now able to handle analog and digital blocks in the same design flow, delivering on a promise made last fall.
Nassda simulator gets analysis tools
News & Analysis  
3/2/2004   Post a comment
Nassda Corp. will announce what it claims is a complete nanometer analysis platform with the release this week of HSIM version 5.0, which adds five optional post-layout analysis tools to the company's HSIM circuit simulator. Nassda is also enhancing the simulator itself.
Silvaco offers open-source Verilog-A models
News & Analysis  
3/2/2004   Post a comment
Moving to help speed adoption of the Verilog-A analog modeling language, Silvaco International is offering nine Verilog-A device models for free download under open-source distribution. The models are compliant with Accellera's Verilog-AMS 2.1 specification. The models include complete source code for BSIM3, BSIM4, EKV, RPI-TFT, Level 3 MOS, Gummel-Poon, Mextram, and diode. Richard Goering reports.
Silvaco offers open-source Verilog-A models
News & Analysis  
3/2/2004   Post a comment
Moving to help speed adoption of the Verilog-A analog modeling language, Silvaco International is offering nine Verilog-A device models for free download under open-source distribution. The models are compliant with Accellera's Verilog-AMS 2.1 specification.
Less costly HW-assisted verification needed
News & Analysis  
3/1/2004   Post a comment
Hardware-assisted verification is crucial, but high costs have slowed adoption. A new approach is needed, says EVE's Luc Burgun.
Nassda simulator gets analysis tools
News & Analysis  
3/1/2004   Post a comment
Nassda Corp. will announce what it claims is a complete nanometer analysis platform with the release this week of HSIM version 5.0, which adds five optional post-layout analysis tools to the company's HSIM circuit simulator.
Virtuoso unifies mixed-signal, analog flows
News & Analysis  
3/1/2004   Post a comment
Cadence Design Systems Inc. will announce this week that its Virtuoso Custom Design Platform is now able to handle analog and digital blocks in the same design flow, delivering on a promise made last fall.
TTL: Too dated for speedy design
News & Analysis  
3/1/2004   Post a comment
The sheets written for current-generation CMOS circuits rely on outmoded TTL performance characteristics that don't reflect the performance of these circuits in high-speed apps. A revamping of data sheets is needed.
Synopsys, Magma deals push EDA envelope
News & Analysis  
3/1/2004   Post a comment
Synopsys Inc. and Magma Design Automation Inc. independently announced major acquisitions last week that signal their willingness to pay dearly to expand beyond traditional electronic design automation markets. But competitors, analysts and investors remained skeptical.
Honeywell, Synopsys to develop rad-hard design flow
News & Analysis  
3/1/2004   Post a comment
Honeywell and Synopsys Inc. agreed to develop methods and tools to support the design radiation-hardened and radiation-tolerant ASICs down to 0.15-micron design rules, Synopsys said Monday (March 1, 2004).
Xilinx revises FPGA design software
News & Analysis  
3/1/2004   Post a comment
Xilinx Inc. said Version 6.2i of its integrated software environment (ISE) for FPGA design taps optimizations that deliver a 40 percent performance boost in Virtex-II Pro FPGAs.
Litho universal data model debated
News & Analysis  
3/1/2004   Post a comment
Debate continues on whether a single universal data model can accelerate the lithography process for ever smaller circuits. A recent panel on design/process integration at SPIE 2004 representing users and EDA vendors offered something between a panel discussion and a staged endorsement of the Silicon Integration Initiative's Universal Data Model program.
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