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Content tagged with Design Tools (EDA)
posted in March 2007
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Patent resolution removes cloud over Magma
News & Analysis  
3/30/2007   Post a comment
With the resolution of a long-running patent dispute with Synopsys, Magma Design Automation is freed from a significant legal expense and a drag on the company's market capitalization.
Patent resolution removes cloud over Magma
News & Analysis  
3/30/2007   Post a comment
With the resolution of a long-running patent dispute with Synopsys, Magma Design Automation is freed from a significant legal expense and a drag on the company's market capitalization.
Mentor Graphics supports new ARM Cortex-M1 processor for FPGAs
Product News  
3/30/2007   Post a comment
Comprehensive portfolio of vendor-independent FPGA design solutions from Mentor Graphics allows engineers to implement the ARM Cortex-M1 processor on any FPGA device.
EVE emulator supports Power Architecture
Product News  
3/30/2007   Post a comment
EVE has introduced direct support for Power Architecture technology in embedded applications.
Cadence and Synopsys announce low power solutions
News & Analysis  
3/30/2007   Post a comment
Both Cadence, supporting the CPF standard and Synopsys, supporting the UPF standard, are moving forward in implementing support for the two competing low-power format standards.
Enea acquisition extends Linux expertise
News & Analysis  
3/30/2007   Post a comment
RTOS specialist Enea AB has bought, for $1.2 million, fellow Swedish software group QiValue Technologies, which specializes in embedded and enterprise Linux development.
Synopsys implements Unified Power Format
News & Analysis  
3/29/2007   Post a comment
Synopsys has announced plans to support the Accellera Unified Power Format (UPF), one of two rival low-power description formats, in its products later this year.
Pragmatic Adoption of Formal Analysis
Design How-To  
3/29/2007   Post a comment
The ability to find bugs can be greatly improved by adopting an assertion based verification (ABV) methodology. ABV is a methodology that uses assertions to increase the productivity and quality of functional verification. ABV provides methods to specify properties and cover points.
Language support expanded for Altium Designer
Product News  
3/29/2007   Post a comment
New Korean language support extends Altium Designer's existing Asian and European language capabilities.
DAC program features automotive electronics
News & Analysis  
3/28/2007   Post a comment
Leveraging the theme of automotive electronics, the Design Automation Conference (DAC) has announced the technical program for the 44th DAC, to be held June 4-8, 2007 in San Diego, Calif.
How to simplify the process of specifying register-maps and auto-generating code and other deliverables
Design How-To  
3/28/2007   Post a comment
In creating run-time configurable slave components, the register-map design pattern is often used; SpectaReg can automate away your register-map headaches.
Understand basics of SPICE environment for circuit analysis and design, Part 2 of 2
Design How-To  
3/28/2007   Post a comment
Get a basic understanding of this vital circuit modeling, simulation, and analysis EDA tool
Altium Designer simplifies third-party FPGA core integration
Product News  
3/28/2007   Post a comment
New time-saving tool enables direct import from Xilinx Core Generator and Altera Megafunction Wizard into Altium Designer.
Keynote: How multicore will reshape computing
News & Analysis  
3/28/2007   Post a comment
Anant Agarwal, MIT professor and keynote speaker at the Multicore Expo, described how multicore architectures will force developers to rethink resource size selection, methods of connecting cores, and programming models.
Xilinx testing out China training program
News & Analysis  
3/28/2007   Post a comment
Xilinx Inc. is spinning up an experimental training program in China that aims to train 1,000 IC and system designers in the coming year to help seed local innovation.
IP revenue: reality tromps wishes.
Blog  
3/27/2007   Post a comment
Mentor introduction of a IP product that provides an entire USB subsystem further indicates that IP belongs in EDA.
Micrium introduces industry's first universal embedded system monitoring tool
Product News  
3/27/2007   Post a comment
uC/Probe-STD from Micrium is a universal tool enabling embedded developers to monitor embedded systems in a live environment.
Cadence preps 'global' PCB routing
Product News  
3/26/2007   Post a comment
New technology from Cadence Design Systems uses graphical interconnect planning to capture pc-board design intent, and a global router to implement complex interconnect structures.
Xilinx simplifies embedded development
Product News  
3/26/2007   Post a comment
Updated EDK 9.1i tool suite supports latest Virtex-5 and Spartan-3A devices and streamlines processing design across all FPGA platforms.
Signal integrity approaches meet the multi-Gbps design challenge
Design How-To  
3/26/2007   Post a comment
Understand how modeling and signal integrity can minimize problems of multi-Gbps data links
Altium supports Altera's new low-cost Cyclone III FPGA family
Product News  
3/23/2007   Post a comment
Altium Designer to include support for Altera's new 65-nm Cyclone III FPGAs.
Synplicity provides cost advantage for Altera's Cyclone III FPGAs
Product News  
3/23/2007   Post a comment
Synplify Pro FPGA synthesis from Synplicity offers area-optimized support for Altera's new low-cost Cyclone III FPGAs.
Altera's Quartus II design software supports Cyclone III FPGAs
Product News  
3/23/2007   Post a comment
The web edition of Altera's Quartus II design software offers free design support for high-density low-cost Cyclone III FPGAs.
Mentor announces synthesis support for Altera's Cyclone III FPGAs
Product News  
3/23/2007   Post a comment
Mentor and Altera have been in close cooperation to ensure Precision Synthesis support for the full range of Cyclone III devices.
Commentary: A new definition of ESL
News & Analysis  
3/23/2007   Post a comment
Grant Martin, chief scientist at Tensilica, proposes a new definition for electronic system level (ESL) design and shows how you can participate in an ongoing discussion about ESL.
Understand basics of SPICE environment for circuit analysis and design, Part 1 of 2
Design How-To  
3/23/2007   Post a comment
Get a basic understanding of this vital circuit modeling, simulation, and analysis EDA tool
Report: 11 percent EDA growth in 2006
News & Analysis  
3/23/2007   Post a comment
The EDA industry grew approximately 11 percent in 2006, and growth will remain strong through 2011, according to a new EDA market forecast report issued by Gary Smith EDA.
US may back down on tech export policy
News & Analysis  
3/23/2007   Post a comment
The U.S. government is taking a second look at controversial plan to tighten export controls on technology shipped to China and is indicating that it may back down
IC routing contest boosts CAD research
News & Analysis  
3/22/2007   Post a comment
An IC global routing contest at the International Symposium on Physical Design (ISPD) this week will help boost IC placement and routing research, and establish a methodology for comparing routers.
Model-Based Metal Fill Optimizes Planarization and Increases Yield
Design How-To  
3/22/2007   Post a comment
Copper interconnect brought challenges to achieving high yield due to effects such as dishing, dielectric erosion and thickness variations caused by Chemical Mechanical Polishing (CMP) during planarization. Model-Based Metal Fill Optimizes Planarization and Increases Yield.
For low-power design, speak two languages
News & Analysis  
3/22/2007   Post a comment
It's looking like the impasse between camps supporting Common Power Format and Unified Power Format means that chip designers will need to familiarize themselves with both or hope that translators can make the task easier.
IC power standards convergence falters
News & Analysis  
3/21/2007   Post a comment
With new developments in the IEEE and the Silicon Integration Initiative (Si2), a short-term convergence between two rival IC low-power specifications "just doesn't seem possible," said Steve Schulz, Si2 president.
Xilinx Delivers PlanAhead 9.1 Design Suite
Product News  
3/21/2007   Post a comment
A new version of the PlanAhead tool from Xilinx supports their latest FPGA device families and includes a new capability. PinAhead allows designers to easily define the chip pinout.
EDA is not dead; change is an indication of life.
Blog  
3/20/2007   Post a comment
Some people are quick to pronoune EDA dead. In fact it is in a period of transition. It can either grow larger than ever or shrink to a quarter of its size.
PlanAhead 9.1 streamlines FPGA design for PCB integration
Product News  
3/20/2007   Post a comment
Xilinx's latest iteration of its PlanAhead hierarchical design and analysis software that supports its 65-nm Virtex-5 and Spartan-3 generation devices has been enhanced with a PinAhead technology, which streamlines FPGA design for PCB integration.
Paper: Fix IC variability post-silicon
News & Analysis  
3/20/2007   Post a comment
A "best paper" at the International Symposium on Physical Design (ISPD) Monday (March 19) proposed a method of fixing IC variability problems post-silicon through the use of tunable clock tree buffers.
CEVA's IP optimizes size, cost of mobile TV chips
Product News  
3/19/2007   Post a comment
Based on the CEVA-X1620 DSP core, the single-processor solutions reduce silicon size and bill of materials.
Reference kit advances CobraNet audio network design
Product News  
3/19/2007   Post a comment
Cirrus Logic Inc. and Stardraw.com Ltd. have teamed up to offer a reference kit that is aimed at helping audio network engineers design CobraNet digital audio networks with custom user interfaces.
Design for Variability
Design How-To  
3/19/2007   Post a comment
At nanometer technologies, variability is rapidly becoming one of the leading causes for chip failures and delayed schedules. However, there is significant confusion about the term "variability" in the design community today.
Commentary: EDA is dead, software lives
Blog  
3/16/2007   Post a comment
With fewer and fewer chips being designed, there's less need for EDA tools and more need for embedded software development, says Paul McLellan, vice president of marketing at Virtutech Inc.
DASC approves low power format PAR
News & Analysis  
3/16/2007   Post a comment
IEEE's Design Automation Standard Committee has approved the Project Authorization Request (PAR) to develop a low-power format standard for use by the EDA industry.
Rockwell seeks 50 percent design cycle reduction
News & Analysis  
3/15/2007   Post a comment
Avionics electronics firm Rockwell Collins is integrating tools and processes at the enterprise level as part of a five-year effort to cut engineering cycle times in half.
Accurate Thermal Analysis of Chip/Package Systems
Design How-To  
3/15/2007   Post a comment
With the increasing complexity and power dissipation of modern electronic designs, controlling peak temperature and predicting the temperature profile on the chip early in the process is becoming critical for insuring system reliability. Low power design methodologies create their own thermal challenges, as they may generate "hot" and "cool" regions on the chip. Causes and soutions are explored.
DFM startup Pyxis shuffles CEOs
News & Analysis  
3/14/2007   Post a comment
EDA veteran Joe Hutt has become president and CEO of design for manufacturability (DFM) startup Pyxis, replacing Naeem Zafar. The move reflects a shift to a more technical leadership, according to Hutt.
Linux OS supports Xilinx MicroBlaze
Product News  
3/13/2007   Post a comment
LynuxWorks has released a new Linux OS, BlueCat Linux Micro Edition (BlueCat-ME), that brings the latest Linux 2.6 kernel to users of Xilinx MicroBlaze embedded processors.
Improve analog/mixed-signal simulator analysis using real-world, hardware-generated data
Design How-To  
3/12/2007   Post a comment
Gain valuable insight by combining simulation with captured, exported data. This tool should be capable of accepting real-world, hardware-generated data acquired using leading-edge instrumentation
Total Power Optimization in RTL-to-GDSII Implementation Flow
Design How-To  
3/12/2007   Post a comment
To properly design a power aware circuit you must manage power from RTL to silicon. This comprehensive article illustrates the relevant technical issues and provides designers with a comprehensive discussion of the issue.
Ciranova places p-cell software in escrow
Product News  
3/12/2007   Post a comment
Ensuring that its PyCell Studio software for generating parameterized cells (p-cells) will always be available and free, startup Ciranova has placed the source code in escrow through the Silicon Integration Initiative (Si2).
ESL tool expands Spirit IP support
Product News  
3/9/2007   Post a comment
Nauet, a low-cost electronic system level (ESL) design tool that generates hardware and software outputs from Spirit XML files, has improved its lint tool and added a Spirit IP-XACT import wizard.
WLAN module, software package tailored for DaVinci-based systems
Product News  
3/8/2007   Post a comment
Mistral Software has put together a software-based WLAN product that will help engineers designing portable wireless devices based on Texas Instruments' DM644x series DaVinci processors accelerate product development.
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