Pragmatic Adoption of Formal Analysis Design How-To 3/29/2007 Post a comment The ability to find bugs can be greatly improved by adopting an assertion based verification (ABV) methodology. ABV is a methodology that uses assertions to increase the productivity and quality of functional verification. ABV provides methods to specify properties and cover points.
Keynote: How multicore will reshape computing News & Analysis 3/28/2007 Post a comment Anant Agarwal, MIT professor and keynote speaker at the Multicore Expo, described how multicore architectures will force developers to rethink resource size selection, methods of connecting cores, and programming models.
Cadence preps 'global' PCB routing Product News 3/26/2007 Post a comment New technology from Cadence Design Systems uses graphical interconnect planning to capture pc-board design intent, and a global router to implement complex interconnect structures.
Commentary: A new definition of ESL News & Analysis 3/23/2007 Post a comment Grant Martin, chief scientist at Tensilica, proposes a new definition for electronic system level (ESL) design and shows how you can participate in an ongoing discussion about ESL.
IC routing contest boosts CAD research News & Analysis 3/22/2007 Post a comment An IC global routing contest at the International Symposium on Physical Design (ISPD) this week will help boost IC placement and routing research, and establish a methodology for comparing routers.
For low-power design, speak two languages News & Analysis 3/22/2007 Post a comment It's looking like the impasse between camps supporting Common Power Format and Unified Power Format means that chip designers will need to familiarize themselves with both or hope that translators can make the task easier.
IC power standards convergence falters News & Analysis 3/21/2007 Post a comment With new developments in the IEEE and the Silicon Integration Initiative (Si2), a short-term convergence between two rival IC low-power specifications "just doesn't seem possible," said Steve Schulz, Si2 president.
Paper: Fix IC variability post-silicon News & Analysis 3/20/2007 Post a comment A "best paper" at the International Symposium on Physical Design (ISPD) Monday (March 19) proposed a method of fixing IC variability problems post-silicon through the use of tunable clock tree buffers.
Design for Variability Design How-To 3/19/2007 Post a comment At nanometer technologies, variability is rapidly becoming one of the leading causes for chip failures and delayed schedules. However, there is significant confusion about the term "variability" in the design community today.
DASC approves low power format PAR News & Analysis 3/16/2007 Post a comment IEEE's Design Automation Standard Committee has approved the Project Authorization Request (PAR) to develop a low-power format standard for use by the EDA industry.
Accurate Thermal Analysis of Chip/Package Systems Design How-To 3/15/2007 Post a comment With the increasing complexity and power dissipation of modern electronic designs, controlling peak temperature and predicting the temperature profile on the chip early in the process is becoming critical for insuring system reliability. Low power design methodologies create their own thermal challenges, as they may generate "hot" and "cool" regions on the chip. Causes and soutions are explored.
DFM startup Pyxis shuffles CEOs News & Analysis 3/14/2007 Post a comment EDA veteran Joe Hutt has become president and CEO of design for manufacturability (DFM) startup Pyxis, replacing Naeem Zafar. The move reflects a shift to a more technical leadership, according to Hutt.
Linux OS supports Xilinx MicroBlaze Product News 3/13/2007 Post a comment LynuxWorks has released a new Linux OS, BlueCat Linux Micro Edition (BlueCat-ME), that brings the latest Linux 2.6 kernel to users of Xilinx MicroBlaze embedded processors.
Ciranova places p-cell software in escrow Product News 3/12/2007 Post a comment Ensuring that its PyCell Studio software for generating parameterized cells (p-cells) will always be available and free, startup Ciranova has placed the source code in escrow through the Silicon Integration Initiative (Si2).
ESL tool expands Spirit IP support Product News 3/9/2007 Post a comment Nauet, a low-cost electronic system level (ESL) design tool that generates hardware and software outputs from Spirit XML files, has improved its lint tool and added a Spirit IP-XACT import wizard.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.