IBM warns of 'design rule explosion' beyond 22-nm News & Analysis 3/31/2010 Post a comment The recent The International Symposium on Physical Design featured a warning from IBM about "design rule explosion," Mentor Graphics' pitch to the automotive sector and a proposal from a former Cadence Design Systems Fellow on using EDA to study the human brain.
RTL synthesis can accelerate the entire implementation flow Design How-To 3/31/2010 1 comment You work in an environment where demanding design goals and aggressive project schedules go hand-in-hand with the push to get more complex products to market faster. And you have just finalized the RTL description of your company's next-generation product, a large system-on-chip (SoC). With just a few weeks remaining for final synthesis, place and route (P&R) and post-layout verification tasks, you wonder: can I still finish the job on schedule?
Target names sales partner in Korea News & Analysis 3/31/2010 Post a comment Target Compiler Technologies NV (Leuven, Belgium) announced it has concluded a distribution agreement with Seoul-based Acetronix to provide sales and marketing support for its IP Designer and IP Programmer EDA tools throughout Korea.
Supreme Court expected to rule on Bilski case soon News & Analysis 3/30/2010 Post a comment Legal experts expect the Supreme Court will issue a decision any day upholding the Bilski ruling that limits business-method and software patents but may call for the Federal Circuit court to broaden a test of what can be patentable it set in that case.
Infineon uses Synopsys' Galaxy for baseband processor Product News 3/30/2010 Post a comment Munich-based chipmaker Infineon Technologies AG said it has deployed Synopsys' Galaxy Implementation Platform, including IC Compiler, for the 40nm processor aimed at the X-GOLD 626 multi-million-gate analog and digital system-in-package (SIP).
Virage, MIPS match memory, processor IP Product News 3/30/2010 Post a comment Processor IP company MIPS Technologies Inc. (Sunnyvale, Calif.) is teaming up with another IP licensor Virage Logic Corp. (Fremont, Calif.) to offer embedded memory IP for joint customers.
Tanner EDA appoints sales partner News & Analysis 3/30/2010 Post a comment Tanner EDA, a division of Tanner Research Inc. (Monrovia, Calif.), has concluded an agreement with New York-based Kelleher Systems for the distribution of its full-flow analog IC design suite, HiPer Silicon, throughout North America.
Synopsys completes CoWare acquisition News & Analysis 3/26/2010 Post a comment EDA and IP vendor Synopsys Inc. (Mountain View, Calif.) announced it has completed the acquisition of electronic system-level design software vendor CoWare Inc. Financial terms of the agreement remained undisclosed.
China cuts 2010 telecom capex by 21 percent News & Analysis 3/24/2010 Post a comment With its 3G binge over, China's three major telecom operators will cut their spending on capital equipment by more than 20 percent in 2010, a greater than expected decline, driving analyst to anticipate lower revenues for system and chip makers including Ericsson.
Mentor, MathWorks roll integrated workflow for DO-254 News & Analysis 3/24/2010 Post a comment Mentor Graphics Corp. and The MathWorks Inc. claimed that they have demonstrated an integrated workflow for DO-254 compliance using Model-Based Design. The objective here is to extend the benefits of Model-Based Design from HDL simulation and analysis through synthesis and implementation.
Self-centric design it's all about you Blog 3/24/2010 Post a comment Call it self-centered design, but obviating the requirement for engineers to go outside of their productive sphere to gather crucial design information delivers strong dividends throughout the design process.
Real reuse for requirements Design How-To 3/23/2010 Post a comment This white paper discusses the elements that make up a requirement and establishes common understanding of how requirements evolve, how that evolution is retained, and how organizations can reuse requirements across projects, products and product lines to accelerate time to market, reduce complexity and cut development costs.
Greening processor design Design How-To 3/22/2010 8 comments For the engineers and designers, delivering a high-performance design, while keeping energy conservation in mind, remains a delicate balance. Fundamental advances at the silicon design level, however, have led to significant improvements in power efficiency for many of these electronics. To that effect in the last few years much of the attention of the industry has been focused on multicore architectures. While this architecture shift has certainly helped address some power concerns, a lesser kn
Analysts cite five growth areas to watch News & Analysis 3/22/2010 Post a comment PC demand is starting off the year better than expected with Acer, Apple and Hewlett-Packard benefiting from the trend, and in smart phones Samsung and LG Electronics are poised for a major push into handsets using Google Android, according to analysts from Barclays Capital.
Cadence acquires FPGA-focused EDA startup News & Analysis 3/22/2010 1 comment EDA vendor Cadence Design Systems, Inc. announced it has acquired Taray Inc. (Campbell, Calif.) to strengthen its position in the design-in of large and complex FPGAs into PC boards. Financial terms remained undisclosed.
Let's fix NASA, then explore the solar system News & Analysis 3/22/2010 4 comments The Obama administration, boxed in by a collapsed global economy and corporate excess, has made the correct, albeit unpopular, decision on reinventing the nation's space agency while providing a needed course correction for manned spaceflight.
Counting down to NASA's reinvention News & Analysis 3/22/2010 Post a comment Standing close to the launchpad-say, 2.5 miles away at the NASA Press Center here-you're aware of your trouser legs flapping against your shins seconds after the space shuttle blasts off.
10 questions to ask when choosing a virtualization solution Design How-To 3/22/2010 2 comments The adoption of virtualization technology is rising, thanks to hardware cost savings, isolation, and footprint reduction. But choosing a virtualization solution can be intimidating, given the variety of architectures and products available. This article attempts to ease the process of selecting a virtualization solution by posing 10 important questions that any embedded engineer or manager should weigh when considering virtualization.
Why hardware designers should switch to Eclipse Design How-To 3/18/2010 2 comments Integrated Development Environments (IDEs) have long been the primary tool for software engineers. Like an airplane cockpit, an IDE is the control center from which the engineer accesses all of the data and tools that he needs.
Analyst: Tabula won't have immediate market impact News & Analysis 3/18/2010 Post a comment Programmable logic startup Tabula turned some heads with the announcement earlier this month of its novel architecture and introduction of its first products this week. But the company poses no immediate threat to the dominance of market leaders Xilinx and Altera, according to a Wall Street analyst.
Analog vendors battle phantom forecasts News & Analysis 3/18/2010 2 comments The analog semiconductor market is in a fragile state with supply and demand in a state of imbalance and spot shortages showing up in certain product areas but some vendors appear to be managing through the difficult situation better than others.
EDA is not enough! Design How-To 3/17/2010 Post a comment Good EDA tools, even combined within well-automated flows, are not enough to produce quality designs, whatever those designs are for software, systems-on-chip (SoCs), integrated circuits (ICs), intellectual property (IP) or embedded systems.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments