Mentor to proceed with bond offering News & Analysis 3/31/2011 Post a comment Despite protests from billionaire financier Carl Icahn and others, EDA vendor Mentor Graphics it would move ahead with a plan to offer up $253 million in convertible bonds through private placement.
Icahn turns up heat on Mentor's board News & Analysis 3/30/2011 5 comments Billionaire financier Carl Icahn lashed out at Mentor Graphics' board of directors for rejecting his $1.9 billion takeover bid and announcing plans to raise up to $253 million through private placement of convertible bonds.
The politics of productivity Blog 3/29/2011 Post a comment Politics and productivity seem to go hand-in-hand in semiconductor R&D organizations, so it's hardly surprising that ostensibly poor performers use politics to avoid scrutiny.
Stratix V User Guide Lite Design How-To 3/29/2011 2 comments Where do you learn the essentials of an FPGA family? Data sheets make your eyes water; User Guides are too large and time-consuming; what’s required is a User Guide Lite…
EDA growth hit double-digits again in Q4 News & Analysis 3/29/2011 Post a comment EDA revenue for the fourth quarter of 2010 totaled nearly $1.51 billion, up 15 percent compared with the third quarter and up 19 percent compared to the fourth quarter of 2009, according to the EDA Consortium.
Understand baluns for highly integrated RF modules Design How-To 3/28/2011 2 comments Using EM simulation and modeling, RF/MMIC engineers can quickly determine the best physical layout for a particular Marchand balun that may fit their HBT and pHEMT push-pull amplifiers, balanced mixers, or any one of numerous applications.
‘Dear God…’ (From the Dog) Blog 3/26/2011 9 comments Over the years I’ve seen a lot of ‘Diaries belonging to the Cat’ and ‘To-do lists for the Dog’ type messages going around the Internet, but this was a new one for me and it made me smile so I thought I’d share it…
DATE 2011 sees higher attendance News & Analysis 3/24/2011 Post a comment Shortly after closing its doors, DATE (Design, Automation & Test in Europe) 2011 has disclosed that the exhibition attendance has increased by 40 percent on a year-over-year basis.
Synopsys rolls next gen DesignWare Data Converter IP Product News 3/23/2011 Post a comment Synopsys Inc. has released the next generation DesignWare Data Converter IP solutions to help designers significantly reduce the area and power dissipation of their system on chips (SoCs), simplify system integration and lower overall silicon cost.
Error messages we can all understand Blog 3/23/2011 14 comments Have you ever been working with a computer when something goes ‘pear-shaped’ and you receive an error message that might be written in Martian for all the good it does you?
The real role of EDA in the Cloud Design How-To 3/23/2011 7 comments That great big storage bucket in the sky – the vast array of networked devices we call ‘The Cloud’ is a growing presence in our lives. Now EDA had to find its place in the Cloud.
The painless path to EWIS compliance Design How-To 3/22/2011 Post a comment The Electrical Wiring Interconnect Systems (EWIS) standard has become a condition of certification for all new commercial aircraft. These compliance requirements can have a huge impact on cost if not anticipated from the very beginning of an aircraft design project. As this article will illustrate, COTS solutions are ready to shoulder much of the designer’s compliance burden.
May you live in interesting times… Blog 3/21/2011 1 comment When change happens, it usually hurts somebody, and that is why the expression ‘May you live in interesting times’ is usually seen as a curse, but I see this as an opportunity for EDA…
Xilinx ships first 28nm Kintex-7 FPGAs Product News 3/21/2011 2 comments A friend at Xilinx just emailed me to say: ‘We shipped parts to two customers on Friday and we’ve posted a video to YouTube – everyone here is ecstatic about how quickly these came in and how well they’re testing.’
What makes an optimal SoC verification strategy Design How-To 3/21/2011 3 comments A typical SoC design for a consumer electronic device will have blocks that can be broadly classified into processors, DSP cores, peripherals, memory controllers, layered bus architectures and analog components. An optimal SoC verification strategy should address all the challenges that would be encountered during the process of verification. It should include answers to these questions: ''what to verify', 'how to verify' and 'are we done'.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments