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Content tagged with Design Tools (EDA)
posted in March 2011
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Mentor to proceed with bond offering
News & Analysis  
3/31/2011   Post a comment
Despite protests from billionaire financier Carl Icahn and others, EDA vendor Mentor Graphics it would move ahead with a plan to offer up $253 million in convertible bonds through private placement.
Fairchild uses DesignWare USB 2.0 nanoPHY IP for OTG transceiver
Product News  
3/31/2011   Post a comment
Fairchild Semiconductor Inc. claimed it has achieved first-pass silicon success for its FUSB2500 UTMI+ Low-Pin Interface USB On-The-Go transceiver chip with Synopsys' DesignWare USB 2.0 nanoPHY IP.
Magma unveils Excalibur-Litho fab analysis framework
Product News  
3/31/2011   Post a comment
Magma Design Automation Inc. has released Excalibur-Litho, a complete fab analysis framework that supports the development and monitoring of advanced lithography solutions.
Icahn turns up heat on Mentor's board
News & Analysis  
3/30/2011   5 comments
Billionaire financier Carl Icahn lashed out at Mentor Graphics' board of directors for rejecting his $1.9 billion takeover bid and announcing plans to raise up to $253 million through private placement of convertible bonds.
Attofarad accuracy for high-performance memory design
Design How-To  
3/30/2011   1 comment
In this article, Mentor Graphics Corp. explains that new parasitic extraction technology can eliminate guardbanding for memory designs
New 3PLD company Tabula secures $108 million in funding
3/30/2011   1 comment
This funding – the largest awarded to a private semiconductor company over the last decade – to support rapid customer adoption of the industry’s first 3D programmable logic devices.
New compression and encryption IP cores for Lattice FPGAs
Product News  
3/30/2011   1 comment
Lattice and Helion Technology have created scalable, resource-efficient compression system IP cores that are particularly well-suited for the wireless microwave backhaul market.
$29.99 breakout boards from Lattice accelerate PLD design and hardware evaluation
Product News  
3/30/2011   1 comment
Three new low-cost I/O breakout boards for the MachXO, ispMACH 4000ZE, and Power Manager II devices provide easy access to I/O pins.
The politics of productivity
3/29/2011   Post a comment
Politics and productivity seem to go hand-in-hand in semiconductor R&D organizations, so it's hardly surprising that ostensibly poor performers use politics to avoid scrutiny.
No longer a startup, EVE aims for top tier of EDA
The Entrepreneurial Engineer  
3/29/2011   Post a comment
Excerpts from an email interview with Dr. Luc Burgun, co-founder and CEO of French hardware/software co-verification technology vendor EVE.
Stratix V User Guide Lite
Design How-To  
3/29/2011   2 comments
Where do you learn the essentials of an FPGA family? Data sheets make your eyes water; User Guides are too large and time-consuming; what’s required is a User Guide Lite…
Yes! FPGAs with optical interfaces are on the way...
3/29/2011   1 comment
Copper PCB interconnect is becoming problematical at higher data rates – the solution FPGA packages with GPIO on the bottom and optical I/O ports in the side…
EDA growth hit double-digits again in Q4
News & Analysis  
3/29/2011   Post a comment
EDA revenue for the fourth quarter of 2010 totaled nearly $1.51 billion, up 15 percent compared with the third quarter and up 19 percent compared to the fourth quarter of 2009, according to the EDA Consortium.
Altera charts new course for FPGA industry with optical innovation
News & Analysis  
3/29/2011   6 comments
Altera shares its vision of the future with optics subsystem embedded in FPGA package thereby eliminating chip-to-chip and chip-to-backplane bandwidth bottlenecks.
MicroBlaze hosts mobile multisensor navigation system
Design How-To  
3/29/2011   3 comments
Researchers used Xilinx’s soft-core processor to develop an integrated navigation solution that works in places where GPS doesn’t.
Bridging the gap between RTL development and design implementation
3/28/2011   4 comments
For the gigascale systems-on-chip, Eyal Odiz, VP of engineering, RTL synthesis and test automation, Synopsys, Inc. outlines the importance of improving predictability of outcomes across the flow to achieve faster design convergence.
Mentor's board rejects Icahn takeover bid
News & Analysis  
3/28/2011   3 comments
The board of directors of EDA vendor Mentor Graphics voted unanimously to reject a $1.9 billion takeover bid made by billionaire financier Carl Ichan last month, Mentor said.
Understand baluns for highly integrated RF modules
Design How-To  
3/28/2011   2 comments
Using EM simulation and modeling, RF/MMIC engineers can quickly determine the best physical layout for a particular Marchand balun that may fit their HBT and pHEMT push-pull amplifiers, balanced mixers, or any one of numerous applications.
Mentor extends TSMC's Reference Flow 11
Product News  
3/28/2011   Post a comment
Mentor Graphics Corp. and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) announced they have collaborated to enrich TSMC's Reference Flow 11 low power verification solutions.
iWatt deploys Magma's Titan to to shorten analog design process
Product News  
3/28/2011   Post a comment
iWatt, Inc., specializing in a power control ICs, has licensed the Titan mixed-signal design platform from Magma Design Automation Inc. to improve analog design and layout productivity and to automate difficult routing tasks analog cell layouts and chip-level assembly.
‘Dear God…’ (From the Dog)
3/26/2011   9 comments
Over the years I’ve seen a lot of ‘Diaries belonging to the Cat’ and ‘To-do lists for the Dog’ type messages going around the Internet, but this was a new one for me and it made me smile so I thought I’d share it…
Book Review: Bill and Dave: How Hewlett and Packard Built the World's Greatest Company by Michael S. Malone
Engineer’s Bookshelf  
3/26/2011   17 comments
Acclaimed journalist Michael S. Malone relates an in-depth story of Bill and Dave and HP based on exclusive access to corporate and private archives, along with hundreds of interviews.
New digital camera whitens teeth, erases wrinkles, and applies makeup
3/25/2011   1 comment
This really is rather amazing. I just saw an article on the website about a digital camera that essentially “Photoshop’s” images on-the-fly…
Stacked and Loaded: Xilinx SSI, 28-Gbps I/O yield amazing FPGAs
Design How-To  
3/25/2011   3 comments
‘More than Moore’ stacked silicon interconnect (SSI) technology and 28-Gbps transceivers lead a new era of FPGA-driven innovations.
STARC assesses Mentor's Calibre xACT 3D extraction tool
News & Analysis  
3/25/2011   Post a comment
Mentor Graphics Corp. announced that the Tokyo-based Semiconductor Technology Academic Research Center (STARC) has disclosed the evaluation results for its Calibre xACT 3D Field Solver extraction tool.
Synopsys deploys MunEDA's WiCkeD tool suite
Product News  
3/25/2011   Post a comment
Synopsys Inc. has integrated the WiCkeD tool suite from MunEDA GmbH (Munich, Germany) in its HSPICE, CustomSim and Galaxy Custom Designer design and simulation environments.
Is that a Geiger counter in your pocket (or are you just happy to see me)?
3/24/2011   9 comments
I was just looking at a really interesting Radiation Dose Chart on the website, which bills itself as “A webcomic of romance, sarcasm, math, and language.”
EE Times Special Edition – Engineers' Career Guide and Salary Survey
3/24/2011   1 comment
OK, who’s not interested in comparative salary studies? For myself, I’m always keen to see how well I’m doing compared to everyone else (so long as I’m not at the bottom of the pile [grin])
The uncertainty principle
Engineering Pop Culture!  
3/24/2011   25 comments
The more we know, the less we know, and that's a problem for electronics and society
DATE 2011 sees higher attendance
News & Analysis  
3/24/2011   Post a comment
Shortly after closing its doors, DATE (Design, Automation & Test in Europe) 2011 has disclosed that the exhibition attendance has increased by 40 percent on a year-over-year basis.
Mentor's next gen emulation PF speeds high-speed Ethernet products verification
Product News  
3/24/2011   Post a comment
Mentor Graphics Corp. has released its next-generation emulation platform to accelerate the verification of 100-Gigabit Ethernet products.
Plan strategies for adopting Model-Based Design for embedded applications: Part 3—Migration plan; requirements and the design phase
Design How-To  
3/24/2011   Post a comment
When transitioning to Model-Based Design for embedded systems development, it is essential to consider an overall plan spanning people, development processes, and tools.
Synopsys rolls next gen DesignWare Data Converter IP
Product News  
3/23/2011   Post a comment
Synopsys Inc. has released the next generation DesignWare Data Converter IP solutions to help designers significantly reduce the area and power dissipation of their system on chips (SoCs), simplify system integration and lower overall silicon cost.
Freescale uses Synopsys' DesignWare IP for SoC designs
News & Analysis  
3/23/2011   2 comments
Freescale Semiconductor Inc. announced it has licensed Synopsys' portfolio of DesignWare interface and analog IP to accelerate system-on-chip (SoC) designs.
Building an HRRG Steampunk Computer – Part 2 – The System Clock
Design How-To  
3/23/2011   21 comments
In Part 1 of this mini- series we introduced the concept of a Heath Robinson Rube Goldberg (HRRG) Steampunk computer. Let’s start by considering the system clock...
Using simulation and emulation together to create complex SoCs
Design How-To  
3/23/2011   Post a comment
Laurent Ducousso, the IP verification manager for ST's HEG, uses EVE's ZeBu emulation platform to verify designs and delivers his observations.
Error messages we can all understand
3/23/2011   14 comments
Have you ever been working with a computer when something goes ‘pear-shaped’ and you receive an error message that might be written in Martian for all the good it does you?
The real role of EDA in the Cloud
Design How-To  
3/23/2011   7 comments
That great big storage bucket in the sky – the vast array of networked devices we call ‘The Cloud’ is a growing presence in our lives. Now EDA had to find its place in the Cloud.
KaiSemi to showcase automated FPGA-to-ASIC flow at ESC Silicon Valley
News & Analysis  
3/22/2011   1 comment
At the forthcoming ESC Silicon Valley, KaiSemi is set to showcase its innovative IP synthesis tool that automatically converts any FPGA netlist directly to ASIC netlist with the push of a button.
DDR2/DDR3 memory controller calibration IP for ASICs and FPGAs
News & Analysis  
3/22/2011   6 comments
Semi IP innovator Uniquify has invented ‘self-calibrating logic,’ whereby the memory controller does a self-test on EVERY power up to select the optimal delay.
The painless path to EWIS compliance
Design How-To  
3/22/2011   Post a comment
The Electrical Wiring Interconnect Systems (EWIS) standard has become a condition of certification for all new commercial aircraft. These compliance requirements can have a huge impact on cost if not anticipated from the very beginning of an aircraft design project. As this article will illustrate, COTS solutions are ready to shoulder much of the designer’s compliance burden.
PHEV charging scheme could ease 'hybrid penalty'
Design How-To  
3/22/2011   11 comments
Plug-in users can mitigate grid demand in exchange for payment, which offsets high Li-ion battery cost.
What’s the best time-travel book/film ever?
3/21/2011   42 comments
I guess I should really start off by being honest and letting you know up front that there’s an underlying motive for this blog, which is…
May you live in interesting times…
3/21/2011   1 comment
When change happens, it usually hurts somebody, and that is why the expression ‘May you live in interesting times’ is usually seen as a curse, but I see this as an opportunity for EDA…
Xilinx ships first 28nm Kintex-7 FPGAs
Product News  
3/21/2011   2 comments
A friend at Xilinx just emailed me to say: ‘We shipped parts to two customers on Friday and we’ve posted a video to YouTube – everyone here is ecstatic about how quickly these came in and how well they’re testing.’
Don’t let analog/digital misinterpretations put your design in jeopardy
Design How-To  
3/21/2011   12 comments
When digital designers meet analog systems, misunderstanding device operation or design requirements results in some fascinating analog horror stories
What makes an optimal SoC verification strategy
Design How-To  
3/21/2011   3 comments
A typical SoC design for a consumer electronic device will have blocks that can be broadly classified into processors, DSP cores, peripherals, memory controllers, layered bus architectures and analog components. An optimal SoC verification strategy should address all the challenges that would be encountered during the process of verification. It should include answers to these questions: ''what to verify', 'how to verify' and 'are we done'.
What’s the number of ASIC versus FPGA design starts?
Design How-To  
3/20/2011   21 comments
One often sees articles that say things like ‘In 2010 there were 2,500 ASIC design starts versus 90,000 FPGA design starts.’ But where do these numbers actually come from and how accurate are they?
ADI changes the game with Circuits from the Lab
Product News  
3/18/2011   6 comments
Designed for fast and easy system integration, ADI’s reference circuits test data, schematics, BOM, layout files, and device drivers
System awareness improves SOC power management
Design How-To  
3/18/2011   3 comments
Understand how power management tactics within a SOC interact with the bigger system-level functions
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