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Content tagged with Design Tools (EDA)
posted in April 2001
Xilinx offers migration kit to Altera customers
News & Analysis  
4/30/2001   Post a comment
Xilinx Inc. (San Jose, Calif.) will introduce an Altera-to-Xilinx design migration kit this week that will allow users of Altera Corp. parts and Max+plus II software to transfer their designs to Xilinx's Integrated Synthesis Environment (ISE) tool flow.
ChipPac offers IC packaging design, analysis service on Web site
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4/26/2001   Post a comment
SANTA CLARA, Calif. -- ChipPac Inc. today announced an automated IC packaging design service that uses the company's Web site and addresses device performance and reliability issues. The design system addresses simulation and analysis of electrical, mechanical, and thermal characteristics.
Silicon foundry PolarFab inks deal with Cadence
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4/25/2001   Post a comment
SAN JOSE -- Silicon foundry PolarFab Inc. and Cadence Design Systems Inc. here announced an electronic design automation tool that will accelerate the manufacturing flow in PolarFab's BiCMOS-based wafer fab. The companies announced the availability of the Process Design Kit (PDK), a product that promises to accelerate the time-to-tapeout for customers. The PDK is based on Cadence's analog, mixed-signal, and radio-frequency (RF) IC design tools.
Zuken folds in Web delivery for analysis software
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4/23/2001   Post a comment
PCB design tools company Zuken is readying the US and European launches of a pay-per-use Web-based design programme for its analysis products. A similar system was launched last week in Japan.
Financial clouds gather over EDA
News & Analysis  
4/19/2001   Post a comment
Cadence Design Systems Inc.'s first-quarter 2001 results sound great on first reading — a 34 percent gain over the same quarter a year ago.
Tality pulls IPO and aims to cut 140 jobs
News & Analysis  
4/19/2001   Post a comment
Cadence subsidiary blames market conditions for postponement of stock offering and plans for profitability.
Denali licenses Rambus controller technology for online design tool
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4/16/2001   Post a comment
PALO ALTO, Calif. -- Denali Software Inc., a supplier of tools for design and verification of memory subsystems, today announced a licensing pact with Rambus Inc. to sell configurable controller technology for modules using Rambus DRAMs.
Timing tool learns to deal with crosstalk
News & Analysis  
4/16/2001   Post a comment
Synopsys has combined its PrimeTime static timing analysis tool with a crosstalk analysis engine. The company decided to combine the two to reduce the time it takes to get information about timing effects caused by crosstalk.
EDP speakers find analog flow lacking
News & Analysis  
4/12/2001   Post a comment
The current analog/mixed-signal design flow has a lot of gaps and is in need of a substantial overhaul, according to speakers at the Electronic Design Processes (EDP) workshop Tuesday (April 10). But the road to a top-down analog design flow won't be an easy one, speakers warned.
Magma lays off almost a quarter of work force
News & Analysis  
4/9/2001   Post a comment
EDA startup Magma Design Automation Inc. has laid off close to 25 percent of its staff, EE Times has learned. Roy Jewell, Magma's new chief operator officer, confirmed the layoffs, but insisted that the company's revenues and backlog remain strong.
MoSys, TSMC to develop double-density and low-power 1T-SRAMs for embedded use
News & Analysis  
4/9/2001   Post a comment
SUNNYVALE, Calif. -- MoSys Inc. here today (April 9) announced a series of new licensing pacts for its 1T-SRAM technology, including a joint-development agreement with Taiwan Semiconductor Manufacturing Co. Ltd. to create new low-power and double-density derivatives of one-transistor memory cells for TSMC's 0.13-micron foundry processes.
TSMC announces 'manufacturability-focused' design reference flow
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4/6/2001   Post a comment
HSINCHU, Taiwan -- Taiwan Semiconductor Manufacturing Co. Ltd. here today (April 6) announced it has worked with design automation partners to create a IC design reference flow that will help accelerate product development by emphasizing "manufacturability" in 0.25- and 0.18-micron processes.
Malaysia's fabless chip company orders design tools, workstations
News & Analysis  
4/5/2001   Post a comment
KUALA LUMPER, Malaysia -- Malaysia Microelectronic Solutions Sdn Bhd (My-MS)--which claims to be Malaysia's first fabless chip company--today (April 5) announced key purchasing agreement with Cadence Design Systems Inc. and Hewlett-Packard Co.
Altera teams with Synplicity to synthesize of SoC cores in programmable logic
News & Analysis  
4/3/2001   Post a comment
SAN JOSE -- Altera Corp. today (April 3) announced a partnership with Synplicity Inc. in nearby Sunnyvale to enhance implementation of intellectual property (IP) functions in programmable logic for system-on-chip applications.
Synopsys goes open source with verification language
News & Analysis  
4/2/2001   Post a comment
Design automation company Synopsys has opened up its Vera verification language but, in contrast to recent moves in the sector, has gone for the open-source route instead of trying to get it adopted by standards bodies.


What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.

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