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Content tagged with Design Tools (EDA)
posted in April 2003
SoC Embedded Memories
Design How-To  
4/28/2003   Post a comment
Complex memories: the art of mixing traditional simulation with innovative verification solutions
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4/28/2003   Post a comment
Today, memory "blocks" occupy an increasing portion of system-on-chip (SoC) designs.
Infrastructure ASICs drive high-performance memory decisions
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4/28/2003   Post a comment
The current generation of networking infrastructure ASICs at the 130-nm process node provides a set of memory challenges that go well beyond the processor-centric designs of the past.
Better memory models support SoC verification tasks
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4/28/2003   Post a comment
While simulation models of standard off-the-shelf memory components have taken leaps and bounds forward with respect to functionality and debug capabilities, embedded memory models have not changed significantly for many years.
Watch out for compatiblity, complexity issues for future embedded Flash
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4/28/2003   Post a comment
With advances in deep submicron CMOS technology, more feature-rich integrated silicon devices are being used in consumer electronics, advanced communication and networking systems, computers, servers and virtually all electronic systems
Enhanced verification vital for embedded memory design
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4/28/2003   Post a comment
Increasing data throughput requirements continue to boost demand for more memory in highly integrated products.
Multi-port memories evolve to meet SoC demands
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4/28/2003   Post a comment
For designers charged with integrating a wide range of functions into system-on-chip (SoC) solutions, the cost and complexity of incorporating digital logic, processing, memory, and analog functions often prove inhibitive.
Memory overwhelms current verification techniques
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4/28/2003   Post a comment
The modern System-on-Chip (SoC) could reasonably be called an island of logic, surrounded by a sea of memory.
Embedded memories multiply inSoCs
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4/28/2003   Post a comment
SRAMs have long been a system-on-chip mainstay, but both the size of the SRAM blocks and the number of them in a single SoC have started to increase explosively in the past year or so.
BIST, BISR tools push up quality, yield
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4/28/2003   Post a comment
Today's nanometer system-on-chip (SoC) designs typically embed a very large number of memories that are extremely sensitive to many different hardware-production defects.
Overcoming timing, power bottlenecks
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4/28/2003   Post a comment
In most SoC designs, embedded ROM, RAM or register file memories of various sizes consume up to 50 percent of die area.
Pressure is on third-party memory IP
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4/28/2003   Post a comment
As chip content grows in complexity, a corresponding, and dramatic, change is occurring in the semiconductor industry.
Making hardware modules firmware-friendly
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4/25/2003   Post a comment
LSI Logic's "firmware friendly" engineer, David Fechser, shows you how to design abstract functional blocks in a way that facilitates firmware implementation.
Design for verification methodology allows silicon success
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4/18/2003   Post a comment
In this detailed whitepaper, Synopsys authors Rindert Schutten and Tom Fitzpatrick set forth a new "design for verification" methodology based on assertions and multi-level interface design. The methodology unites dynamic and formal tools, and leverages verification IP.
Synthesizable analog IP key to embedded SoC platforms
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4/18/2003   Post a comment
Perhaps, the most compelling new trend in system-level embedded design is the concept of application "platforms".
ASIC/ASSP platform speeds development
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4/18/2003   Post a comment
As technology advances, system-on-chip devices tend to absorb and integrate more functionality from surrounding systems. It is rapidly becoming impossible to develop an SoC from scratch: The amount of knowledge and experience required of the design team would make the project unmanageable, prohibitively expensive or would increase the design time so much that the device would be obsolete before its introduction.
Method offers snapshot of SoC operation
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4/18/2003   Post a comment
With an ever-shortening development cycle, and often several generations of products being produced in parallel or in rapid succession, the need for standardized embedded tools and capabilities that enable quick analysis and debug of embedded intellectual property (IP) is a critical factor in keeping system-on-chip verification manageable.
Current Chip Design Flow is Flawed
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4/14/2003   Post a comment
As in any other engineering activity, the design of semiconductor chips (ICs) encompasses several separate, but often closely coupled, design activities. Today's SoC development exemplifies such a design flow, comprising tasks such as design conceptualization, architectural design and optimization, logic synthesis, physical implementation, and design verification. Evolving design tools and design methodologies require changes in software design-tool capabilities to meet current and future chip
How performance analysis aids system design
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4/11/2003   Post a comment
Mentor Graphics' Jim Kenney shows how designers can use performance analysis to analyze system throughput and look for bottlenecks that affect CPU time, memory, and bus utilization.
How Tensilica verifies processor cores
News & Analysis  
4/4/2003   Post a comment
How does Tensilica pre-verify a large number of possible configurations for its Xtensa processor core? Tensilica's Dhanendra Jain and Steve Leibson describe a verification methodology built around tools from multiple vendors.


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