Multi-port memories evolve to meet SoC demands Design How-To 4/28/2003 Post a comment For designers charged with integrating a wide range of functions into system-on-chip (SoC) solutions, the cost and complexity of incorporating digital logic, processing, memory, and analog functions often prove inhibitive.
Embedded memories multiply inSoCs Design How-To 4/28/2003 Post a comment SRAMs have long been a system-on-chip mainstay, but both the size of the SRAM blocks and the number of them in a single SoC have started to increase explosively in the past year or so.
Design for verification methodology allows silicon success Design How-To 4/18/2003 Post a comment In this detailed whitepaper, Synopsys authors Rindert Schutten and Tom Fitzpatrick set forth a new "design for verification" methodology based on assertions and multi-level interface design. The methodology unites dynamic and formal tools, and leverages verification IP.
ASIC/ASSP platform speeds development Design How-To 4/18/2003 Post a comment As technology advances, system-on-chip devices tend to absorb and integrate more functionality from surrounding systems. It is rapidly becoming impossible to develop an SoC from scratch: The amount of knowledge and experience required of the design team would make the project unmanageable, prohibitively expensive or would increase the design time so much that the device would be obsolete before its introduction.
Method offers snapshot of SoC operation Design How-To 4/18/2003 Post a comment With an ever-shortening development cycle, and often several generations of products being produced in parallel or in rapid succession, the need for standardized embedded tools and capabilities that enable quick analysis and debug of embedded intellectual property (IP) is a critical factor in keeping system-on-chip verification manageable.
Current Chip Design Flow is Flawed Design How-To 4/14/2003 Post a comment As in any other engineering activity, the design of semiconductor chips (ICs) encompasses several separate, but often closely coupled, design activities. Today's SoC development exemplifies such a design flow, comprising tasks such as design conceptualization, architectural design and optimization, logic synthesis, physical implementation, and design verification. Evolving design tools and design methodologies require changes in software design-tool capabilities to meet current and future chip
How Tensilica verifies processor cores News & Analysis 4/4/2003 Post a comment How does Tensilica pre-verify a large number of possible configurations for its Xtensa processor core? Tensilica's Dhanendra Jain and Steve Leibson describe a verification methodology built around tools from multiple vendors.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments