How to manage a derivative SoC project News & Analysis 4/30/2004 Post a comment Designing derivative systems-on-chip can save a great deal of time, but only if you have a good physical design flow in place. ReShape's Lane Albanese (right) presents a "design maturity" workflow model that will help design teams develop realistic plans, assemble resources, and measure progress.
Moving from Vera to SystemVerilog 3.1 News & Analysis 4/30/2004 Post a comment Making the transition from a language such as Vera to SystemVerilog 3.1 will require a translation strategy and enforcement of coding guidelines, says VeriEZ president and CEO Sashi Obilisetty.
Denali offers PCI Express compliance suite News & Analysis 4/29/2004 Post a comment Promising to save man-years of effort for PCI Express verification, Denali Software is introducing PureSuite, a compliance test suite with some 7,500 pre-built tests. It works with PureSpec, Denali's existing verification intellectual property (IP) for PCI Express.
Focus-On: Standards for test coverage reports Product News 4/29/2004 Post a comment Industry efforts are under way to develop a standard method for reporting test coverage, with the goal of having a reporting standard for stuck-at faults ready in time for next year's International Test Conference.
Synopsys tight-lipped about MoSys lawsuit News & Analysis 4/29/2004 Post a comment Faced with a breach-of-contract suit from spurned partner Monolithic System Technology Inc., Synopsys Chairman and CEO Aart de Geus is revealing little about why Synopsys terminated its controversial merger with MoSys.
Legal woes force Aptix into Chapter 11 protection News & Analysis 4/29/2004 Post a comment A failed lawsuit has forced Aptix Corp., a provider of rapid prototyping systems, into Chapter 11 bankruptcy, EE Times has learned. Coming on the heels of the imprisonment of its former CEO, Aptix was granted Chapter 11 protection after being unable to pay court-ordered fees to Cadence Design Systems.
Bad signals interfere with 90-nm designs News & Analysis 4/28/2004 Post a comment When Agilent Technologies Inc.'s ASIC products division first moved from 130- to 90-nanometer chip design, it got a nasty surprise. "Signal integrity," said Jay McDougal, microprocessor design methodology manager at Agilent, "was really an order of magnitude worse."
McDougal's experience seems to track with that of other users and matches what EDA vendor representatives are saying. Such problems as crosstalk-induced delays, crosstalk-induced glitches and power noise due to voltage drop are all
Synopsys keynoter cites crosstalk, power challenges News & Analysis 4/28/2004 Post a comment Crosstalk and power are extremely difficult problems to solve, and will require significant changes to the existing chip design flow, according to Li-Pen Yuan, R&D director for extraction and signal integrity at Synopsys. Yuan offered a keynote speech at the Electronic Design Processes (EDP-2004) methodology conference here Monday (April 26). Richard Goering was there.
Synopsys keynoter cites crosstalk, power challenges News & Analysis 4/27/2004 Post a comment Crosstalk and power are extremely difficult problems to solve, and will require significant changes to the existing chip design flow, according to Li-Pen Yuan, R&D director for extraction and signal integrity at Synopsys. Yuan offered a keynote speech at the Electronic Design Processes (EDP-2004) methodology conference Monday (April 26).
Bad signals interfere with 90-nm designs News & Analysis 4/26/2004 Post a comment When Agilent Technologies Inc.'s ASIC products division first moved from 130- to 90-nanometer chip design, it got a nasty surprise. "Signal integrity," said Jay McDougal, microprocessor design methodology manager at Agilent, "was really an order of magnitude worse."
MoSys files suit to force Synopsys merger News & Analysis 4/24/2004 Post a comment As expected, Monolithic Systems Technology Inc. (MoSys) is seeking a shotgun wedding, having filed a breach of contract lawsuit Friday (April 23) against Synopsys Inc. for that company's last-minute termination of its acquisition of MoSys one week before.
How specifications drive analog design News & Analysis 4/23/2004 Post a comment Spec-driven design can make it easier to build analog ICs. Architects from Cadence Design Systems, including Tina Najibi (right), show how designs, test cases, and behavioral models can all be created from specifications, and discuss automatic spec import and comparison.
A better route to IC closure News & Analysis 4/23/2004 Post a comment Timing and signal-integrity closure with existing EDA tools is too cumbersome. What's needed is an integrated design process that can concurrently build and analyze a design, says Silicon Design Systems' Naeem Zafar.
Mentor revenue, bookings up; earnings decline News & Analysis 4/23/2004 Post a comment Providing further evidence that the semiconductor industry recovery is trickling down to the EDA industry, Mentor Graphics Corp. announced a 3 percent year-to-year revenue growth, while bookings climbed 17 percent to provide a first quarter bookings record for the company.
Improved Cadence results suggest EDA rebound News & Analysis 4/22/2004 Post a comment Cadence Design Systems posted nearly flat year-to-year revenues and a $9 million loss in the first quarter of 2004, but it's a significant upward trend following a period of declining revenues. Coming in what is the EDA industry's weakest calendar quarter, the uptick may indicate that the semiconductor rebound is trickling down to EDA.
IC buffering panel pits 'chickens' vs. 'ostriches' News & Analysis 4/21/2004 Post a comment A panel billed as "the great IC buffering debate" at the International Symposium on Physical Design (ISPD '04) April 19 examined the positions of "Chicken Littles" who anticipate a buffering crisis, and "ostriches" who believe it can be avoided. While dominated by ostriches, the panel agreed that new approaches to chip design are needed soon.
'Unbelievable' paper cites 90X IC placement speedup News & Analysis 4/20/2004 Post a comment An IC placement paper described as "unbelievable" by conference organizers yet credible, because its results can be duplicated is the talk of this week's International Symposium on Physical Design (ISPD '04) here. The paper, which describes a placement technique that's 97 times faster than a well-known academic placer, could have a profound impact on IC CAD tools.
VIP verifies PCI Express News & Analysis 4/20/2004 Post a comment Denali's verification IP (VIP) for PCI Express includes PureSpec, which is like a "bus functional model on steroids." Here's a detailed view of how the solution works.
Timing optimization rolls for logic designers News & Analysis 4/19/2004 Post a comment Tool startup Silicon Dimensions Inc. has released an add-on to its Chip2Nite floor planner, block design and analysis offering that will let logic designers repair physical defects and do timing optimizations before handing off a design to a physical-design team, the company said.
Synopsys terminates MoSys acquisition plans News & Analysis 4/17/2004 Post a comment One of the most costly and controversial proposed acquisitions in EDA industry history came to a sudden end Saturday (April 17), as Synopsys announced that it has terminated its plans to acquire embedded memory provider Monolithic System Technology (MoSys). Although Synopsys offered no reasons, the termination follows a lawsuit filed against MoSys earlier this month.
An FPGA primer for ASIC designers News & Analysis 4/15/2004 Post a comment If you're used to ASIC design, FPGAs require a new way of thinking, says Rafey Mahmud (right), software applications engineer at Altera. In this feature article, Mahmud highlights what's different in the FPGA design flow, and describes some of the nuances with respect to gated clocks and PLLs.
Mentor links SystemC to emulation News & Analysis 4/15/2004 Post a comment Moving logic emulation to higher levels of abstraction, Mentor Graphics Thursday (April 15) announced a "transaction based" interface between SystemC testbenches and its VStation emulators. The interface is a new feature of the VStation TBX verification accelerator.
DAC offers scholarships to unemployed engineers News & Analysis 4/15/2004 Post a comment The Design Automation Conference (DAC) announced Wednesday (April 14) that it will award scholarships to up to 15 engineers "without personal resources or corporate support." The scholarships will cover admission to the technical program of the 41st DAC, scheduled for June 7-11 in San Diego, Calif.
Consultant begins work on EDA 'encyclopedia' News & Analysis 4/14/2004 Post a comment Seeking to write the definitive book about EDA, consultant and EDA veteran Tom Jackson is working with Kluwer Academic Publishers to compile what he calls an EDA "encyclopedia." Jackson is seeking industry input for his ambitious project, which aims at providing a single reference source that covers the entire EDA industry.
Digital alternative posed to conventional RF News & Analysis 4/12/2004 Post a comment Designers of radio circuits on advanced CMOS processes at Texas Instruments Inc. have recognized a new paradigm: In a deep-submicron CMOS process, the time-domain resolution of a digital signal edge transition is superior to the voltage resolution of analog signals.
Computational microwave circuits arrive News & Analysis 4/12/2004 Post a comment A new class of microwave circuits has emerged recently, partially as a result of the increase in operational frequency of mixed-signal CMOS and BiCMOS technologies, and partially from the introduction of computationally generated modulation schemes, such as the orthogonal frequency-division-multiplexed scheme used in 802.11a wireless LANs.
RF CMOS challenges in SoC Implementation News & Analysis 4/12/2004 Post a comment Designers creating the analog/RF portion of system-on-chip designs need considerable additional support from the foundry. Take one simple component, the inductor, to illustrate the depth of these needs.
Modeling high-speed analog-to-digital converters News & Analysis 4/12/2004 Post a comment During the last three years, the mixed-signal system-on-chip (SoC) market has grown consistently. Industry analyst firm IBS Corp. estimates that by 2006, more than 70 percent of all SoCs will contain some analog components.
New BSIM3 model aids high-voltage IC design News & Analysis 4/9/2004 Post a comment Silvaco International has rolled out a High-Voltage IC Design tool suite for products such as LCD drivers, TFT drivers, and power management ICs. At the heart of the suite is a new BSIM3 level-88 Spice model that offers additional parameters for such effects as self-heating and asymmetric behavior.
Startup takes a novel design-for-yield approach News & Analysis 4/9/2004 Post a comment With a mission of improving semiconductor yields for nanometer-scale ICs, startup Anchor Semiconductor Inc. has quietly begun shipments of NanoScope, a tool that provides full-chip, post-resolution-enhancement technology verification.
Ansoft offers signal-integrity solution News & Analysis 4/8/2004 Post a comment Expanding its Ansoft Designer platform, Ansoft has announced DesignerSI, a signal-integrity design environment for high-speed boards and systems. It works with Nexxim, the company's recently announced circuit simulator.
A look inside behavioral synthesis News & Analysis 4/8/2004 Post a comment Curious about behavioral synthesis? In this article, Forte Design Systems' Michael Meredith (right) explains how it differs from RTL design, and reviews the phases of the behavioral synthesis process, using a simple algorithm as an example.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments