Stanford kicks off parallel programming effort News & Analysis 4/30/2008 2 comments Six companies are contributing a total $6 million to kick off a three-year project at Stanford University to explore fresh models for parallel programming, one of three efforts recently funded by a computer industry increasingly concerned software will not be able to keep pace with the evolution of multicore processors.
Embedded developers cautious on multicore Design How-To 4/30/2008 3 comments Embedded systems developers will make a slow transition to multicore processors, driven by the need for performance but concerned about difficulty programming the new chips and a lack of software standards, according to a survey taken by Virtutech and Freescale at the Embedded Systems Conference in San Jose.
Sony Ericsson project combines Java, Flash Lite for mobiles News & Analysis 4/30/2008 Post a comment Sony Ericsson will demonstrate at next week's JavaOne developers' event in San Francisco its Project Capuchin, which will allow software developers to create applications for mobile phones that can use pieces of both Java ME and Adobe Systems' Flash Lite to create their applications.
Cadence boosts analog verification performance News & Analysis 4/29/2008 Post a comment Against the background of ever-increasing complexity in integrated circuit design, Cadence on its house fair Cadence Live EMEA 2008 introduced a major upgrade to its Virtuoso design platform. The enhancement aim at typical European user environments, centering on performance improvement in the verification of large analog designs.
Development tool supports Stellaris MCUs with USB Product News 4/23/2008 Post a comment Code Red Technologies, a developer of software development tools for 32-bit MCUs, and Luminary Micro, creators of the Stellaris Cortex-M3-based MCUs, announced the immediate availability of Red Suite v1.5 development tools for the Stellaris MCUs featuring USB.
What floorplan information is needed for synthesis Design How-To 4/22/2008 Post a comment Creating custom wireloads based on a trial place-and-route is ineffective, because once synthesis begins structuring logic differently the logic structure - and therefore the placement and routing topology " will be different from the first model.
SPICE and all things nice Blog 4/21/2008 Post a comment I have just been updating myself on the current state of play in the analog EDA world. Whilst my efforts may or may not have been worthwhile, time will tell, one consideration struck me; just what made SPICE so enduring and successful?
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments