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Content tagged with Design Tools (EDA)
posted in April 2013
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EDA/IP weekly roundup – April 10th2013
4/10/2013   Post a comment
Altera, ARM, Cadence, Chenming Hu, Cypress Semi, IC Insights, Imperas, Kathryn Kranen, Mentor, Si2 and TSMC made the lineup today. See here for their news…
Cypress spins low-cost PSoC 4 dev board
Product How-To  
4/10/2013   7 comments
Element 14 is taking orders for the PSoC 4 Pioneer Kit from Cypress Semiconductor, which costs $25 and comes with the Creator integrated design environment.
Altium Designer meets wireless Propeller Beanies at Design West
Design How-To  
4/9/2013   1 comment
In order to create the CapNet wireless propeller beanies, David Ewing first had to learn how to use Altium Designer to capture his schematics and layout his PCB.
Xilinx announces Real-Time Video Engine 2.1
Product News  
4/8/2013   Post a comment
The RTVE 2.1 reference design allows for multiple video processing pipelines, running at 10-bit color depth and full 4:4:4 color subsampling.
Altera demos 32-Gbps transceiver with leading-edge 20nm device
Product News  
4/8/2013   Post a comment
Demonstration highlights latest success in Altera's 20nm FPGA early access program.
A low risk, high reward approach to adopting formal methods
Design How-To  
4/8/2013   Post a comment
At STMicroelectronics, we recently investigated using formal methods as a complement to the constrained random testing of our ARM based CPU subsystems. We verified in four engineering weeks what had taken six engineer weeks of constrained random test-bench development effort…
Learning electronics with the Arduino
4/5/2013   6 comments
There's always something unexpected going on here in the Pleasure Dome (my office). Just a few days ago, for example, I received an email from Don Wilcher…
What were they thinking: no transparency
Engineering Investigations  
4/5/2013   3 comments
I am getting on my soapbox today to complain about the way tickets are sold for large concerts. This may not be true where you are but this is the way it is done in Portland…
The "Top 10" worst computers of all time
4/5/2013   26 comments
Have you ever owned a computer that made you want to pull your hair out?
Ajoy Bose – transitions and the creation of Atrenta
4/4/2013   1 comment
How do you go from working for Bell Labs to starting up a number of EDA companies? Atrenta’s Ajoy Bose tells of his transitions from the largest to the smallest of companies and what he learned along the way…
Your chance to win a wireless mesh networked propeller beanie
Programmable Logic DesignLine Blog  
4/4/2013   5 comments
The folks at Synapse Wireless are offering everyone the chance to win a free wireless mesh networked propeller beanie.
Analog Devices Design Conference 2013 boasts experts from ADI, Xilinx, and MathWorks
Programmable Logic DesignLine Blog  
4/4/2013   Post a comment
Global design conferences connect attendees with high-performance signal processing experts from ADI, Xilinx, and MathWorks.
Father of the FinFET lands Kaufman award
Design How-To  
4/4/2013   8 comments
Professor Chenming Hu of the University of California Berkeley and a former CTO at foundry TSMC has been selected to receive the 2013 Phil Kaufman Award for his contribution to electronic design.
Jasper's Kranen wins ACE lifetime achievement award
Design How-To  
4/4/2013   4 comments
Kathryn Kranen, president and CEO of EDA company Jasper Design Automation Inc., has been announced as the winner of the 2013 ACE Lifetime Achievement Award.
Fairchild enhances Power Supply WebDesigner
Product News  
4/3/2013   Post a comment
The online design and simulation tool now provides CCM, non-isolated PFC buck and buck LED driver designs in under a minute.
Xilinx Vivado Design Suite boasts IP integration and HLS enhancements
Product News  
4/3/2013   Post a comment
Latest release of the Vivado SoC-strength design suite introduces IP Integrator and High-Level Synthesis enhancements.
EDA/IP weekly roundup – April 3rd 2013
4/3/2013   Post a comment
Accellera, ARM, Asset, Digital Core, EDAC, FishTail, Gartner, GlobalFoundries, ProPlus, Silicon Labs, TSMC and Xilinx made the lineup today. See here for their news…
Rethinking communications: Automating tapeout review reporting
4/2/2013   Post a comment
Tapeout of a chip is a collaboration between the design house and the foundry. Replacing manual error reporting with an automated reporting capability provides a number of benefits to both the report generator and the report recipient.
DI2CMS – I2C master/slave bus interface from Digital Core Design
Product News  
4/2/2013   Post a comment
Digital Core Design, an IP Core and System-on-Chip design house from Poland, has introduced its newest I2C Bus Interface soft core for ASICs and FPGAs.
What’s next for Raspberry Pi, the dessert of choice for engineers and makers alike?
Design How-To  
4/2/2013   2 comments
The dessert of choice for engineers will be involved in many more projects and applications that will emerge during 2013.
London Calling: The curious incident of the EDA dog food
4/2/2013   1 comment
Some similes and metaphors capture the imagination and resonate for years after they were first uttered.
IP reuse requires both design reuse and verification reuse
4/2/2013   Post a comment
In this era of ever shrinking time to market windows, for semiconductor organizations to win the race to market, they must master IP-based design, and in particular IP reuse encompassing both design and verification reuse...
Global EDA sales ended 2012 with record quarter
Design How-To  
4/2/2013   Post a comment
Demand for EDA tools and services continued to be strong in 4Q12 taking an annual growth run into its 12th consecutive quarter and setting record revenue.
The best electronics-related April Fools' spoof ever?
Programmable Logic DesignLine Blog  
4/1/2013   59 comments
Over the years I've seen a bunch of really great April Fools' day spoofs.
Reclaiming lost yield through methodical power integrity optimization
Design How-To  
4/1/2013   Post a comment
You might be meeting your yield acceptance requirements. But you may still not be getting the most from your manufacturing due to effects of dynamic power and power noise integrity in your design. However, design optimization methodologies are available to reclaim the recoverable yield loss...
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