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Content tagged with Design Tools (EDA)
posted in May 2000
Altera buys PLD place and route tool vendor
News & Analysis  
5/8/2000   Post a comment
Altera Corp. picked up some new place and route tools and some EDA brain power Monday (May 8), buying a tiny PLD place and route company, Right Track CAD (Toronto). Financial details of the purchase were not disclosed.
Simplex tool eyes power-grid electromigration
News & Analysis  
5/8/2000   Post a comment
Simplex Solutions Inc. has tailored the new version of its VoltageStorm power grid and electromigration analysis system for system-on-chip (SoC) design.
Xilinx tunes tools for big FPGAs
News & Analysis  
5/8/2000   Post a comment
FPGA tools will draw a step closer to their ASIC counterparts this week, when Xilinx Inc. releases a version of its Alliance Series software aimed at helping users efficiently design with multi- million-gate FPGAs.
Silicon Metrics adds timing sign-off
News & Analysis  
5/8/2000   Post a comment
IC characterization provider Silicon Metrics Corp. will roll out this week a product line based on its SiliconSmart Models. Included in the lineup is the company's first offering for logic designers—a timing sign-off tool that can extend the accuracy of static timing analyzers.
Avanti criminal charges dismissed
News & Analysis  
5/1/2000   Post a comment
One of the longest-running and most-watched criminal cases in the electronics industry has come to an apparent halt, as a Santa Clara County court judge dismissed all criminal charges against executives of Avanti Corp. on procedural grounds. While the district attorney will seek an appeal, and may re-convene a grand jury to seek new indictments, any new trial date is at least months away.


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What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.

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9/25/2016
4:48:30 PM
michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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