Understanding the "e" verification language News & Analysis 5/29/2003 Post a comment Verisity's "e" language is still proprietary, but Verisity engineer Zeev Kirshenbaum reveals new details about the language in this first-of-its-kind tutorial. Using an Ethernet networking device as an example, the article shows how to build a verification environment using "e."
Consortium Vows to Simplify IP Reuse in SoCs News & Analysis 5/29/2003 Post a comment A group of EDA, silicon intellectual property (IP) and semiconductor vendors will announce the formation of a consortium at the 40th Design Automation Conference (DAC) that will work to facilitate the integration of IP blocks into SoC designs. The consortium is believed to be working on ways to define "metadata" that goes beyond simple I/O information for IP blocksb
Leakage Current Leads 90-nm Rogues' Gallery News & Analysis 5/29/2003 Post a comment As leakage current shoulders its way to center stage in chip designers' gallery of horrors, leading-edge design teams are rapidly developing ad hoc techniques to minimize its impact. And while the EDA industry is characteristically lagging the leading-edge need, at least one vendor is moving aggressively to catch up, formulating both a tool and a methodology for reducing a specific source of leakage current.
Advances in System-Level Design Roll Out News & Analysis 5/23/2003 Post a comment The electronic system-level (ESL) software market will expand this week as Future Design Automation Corp. rolls out a C-language synthesis system and Summit Design Inc. adds hardware/software co-design to its graphical Visual Elite tool. On the hardware side, Axis Systems Inc. is boosting its ESL verification capability with a new model compiler for emulation
Design rules push SoC packaging to the forefront Design How-To 5/23/2003 Post a comment The rise of system-on-chip devices, along with the challenge of 130nm design rules and the looming challenge of 90nm design rules has, and will continue to, test old methodologies and, more often than not, force them into retirement.
Co-design or bust: SoC FBGA packaging News & Analysis 5/23/2003 Post a comment SoC designs require the integration of digital signal processor cores, custom logic, memory and analog on a single chip. Consequently, these designs require signal integrity of critical nets, and adequate power distribution in both the chip and the package.
An overview of SystemVerilog 3.1 Design How-To 5/21/2003 1 comment SystemVerilog 3.1 adds a number of features to the Verilog-2001 standard that facilitate modeling and verification of large systems. In this tutorial, consultant Stu Sutherland provides an overview of some of the more significant new features, and argues that SystemVerilog is ready for adoption and use.
Directives tune 'C' for hardware design Design How-To 5/16/2003 Post a comment Semantics for hardware concepts such as parallelism, timing, and synchronization are not native to C, but they can be added with simple directives. Rich Edelman, applications engineer at Future Design Automation, shows how in this tutorial article.
Forging a Brighter Future in High Tech Design How-To 5/15/2003 Post a comment Technical conferences continue to be one of the best and most cost-effective mechanisms for fostering these close relationships and finding out what other organizations are doing. Ian Getreu, the General Chair of the 40th Design Automation Conference (DAC) provides a preview of the show in Anaheim, CA from June 2-6.
Synopsys Tips 'Hybrid' Formal Verification News & Analysis 5/14/2003 Post a comment Claiming a new approach to functional RTL verification, Synopsys Inc. this week will announce a hybrid product that combines a formal property-checking capability with the company's VCS Verilog simulator. By including the simulation engine, Magellan can reach thousands of cycles deep into designs and avoid the false-negative errors that plague other formal tools, Synopsys said.
Recycle RTL test benches to verify Transaction-Level IP Models News & Analysis 5/13/2003 Post a comment System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an open-source, standard design and verification language written in C++, offers a way to explore different architectures, evaluate algorithms, partition hardware and software tasks, and develop software.
How to generate at-speed scan vectors News & Analysis 5/9/2003 Post a comment At-speed testing is needed to detect many kinds of defects, says Bob Neil, consulting engineer at design services firm Paradigm Works. In this tutorial, he compares approaches used by DFT tools to generate at-speed vectors.
Design for Verification Methodology Allows Silicon Success News & Analysis 5/9/2003 Post a comment Emerging design and verification technologies have shown great promise towards bridging the verification divide that exists in today's complex-chip design projects. However, the lack of a cohesive, efficient methodology to allow these tools and techniques to be utilized efficiently has held back much of the potential progress.
In conjunction with unveiling of EE Times’ Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. One of Silicon Valley's great contributions to the world has been the demonstration of how the application of entrepreneurship and venture capital to electronics and semiconductor hardware can create wealth with developments in semiconductors, displays, design automation, MEMS and across the breadth of hardware developments. But in recent years concerns have been raised that traditional venture capital has turned its back on hardware-related startups in favor of software and Internet applications and services. Panelists from incubators join Peter Clarke in debate.